Spartan-3A DSP: Constraining skew across ODDR2 outputs
I have an application on a Spartan-3A DSP where I generate DDR outputs to a DAC. The receiving DAC is source-synchronous, and I use an array of ODDR2 elements to output the data and a single ODDR2 to generate a matched output clock for the receiving device. The ODDR2 elements are clocked via an external input clock fed to a DCM which generates 0 degree and 180 degree clocks.
It's not clear to me how I specify constraints in order to restrict the skew across these pads: when using the constraints editor I only have the option to select the external input clock, and not the derived clocks out of the DCM. Also, the general procedures for restricting skew between outputs (rather than specifying an offset from an input clock) is not clear.
I'd appreciate it if somebody could briefly explain the methodology or point me in the right direction in the documentation. Sorry if this is a rather basic question...