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Registered: ‎06-02-2020

Spartan 6 Microblaze timing failure


I've been given responsibility of an old Spartan 6 Microblaze design, which needs a few RTL updates. The design seems to be at a tipping point where a small change causes a very long build time. It's gone up from approximately 1h to 3h and now it seems to be failing altogether, in the sense that it doesn't meet timing.

Any general ideas on what to do in a situation like this? The failing endpoint seems to be part of a Fast Simplex Link in the MB system. See below. 


Design info

Tool: ISE 14.1
Device: xc6slx45, package fgg484, speed -2
Input clock: 25 MHz
System clock: 75 MHZ (from Clock generator IP in MB)

Endpoint with largest negative slack:

Paths for end point system_i/sum_data_0/sum_data_0/i_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ (SLICE_X26Y80.D6), 122 paths
Slack (setup path):     -0.884ns (requirement - (data path - clock path skew + uncertainty))
  Source:               system_i/sum_data_0/sum_data_0/i_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0 (FF)
  Destination:          system_i/sum_data_0/sum_data_0/i_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ (FF)
  Requirement:          13.333ns
  Data Path Delay:      14.049ns (Levels of Logic = 4)
  Clock Path Skew:      -0.055ns (0.709 - 0.764)
  Source Clock:         clk75 rising at 0.000ns
  Destination Clock:    clk75 rising at 13.333ns
  Clock Uncertainty:    0.113ns

  Clock Uncertainty:          0.113ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.214ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: system_i/sum_data_0/sum_data_0/i_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0 to system_i/sum_data_0/sum_data_0/i_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X26Y53.AQ      Tcko                  0.525   system_i/sum_data_0/sum_data_0/i_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>
    SLICE_X52Y125.C1     net (fanout=3074)     6.839   system_i/sum_data_0/sum_data_0/i_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>
    SLICE_X52Y125.C      Tilo                  0.255   system_i/sum_data_0/sum_data_0/i_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/
    SLICE_X46Y104.C6     net (fanout=1)        2.017   system_i/sum_data_0/sum_data_0/i_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/
    SLICE_X46Y104.C      Tilo                  0.235   system_i/sum_data_0/sum_data_0/i_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/
    SLICE_X26Y80.B5      net (fanout=1)        2.877   system_i/sum_data_0/sum_data_0/i_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/
    SLICE_X26Y80.B       Tilo                  0.254   system_i/sum_data_0/sum_data_0/i_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/<11>
    SLICE_X26Y80.D6      net (fanout=1)        0.598   system_i/sum_data_0/sum_data_0/i_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/
    SLICE_X26Y80.CLK     Tas                   0.449   system_i/sum_data_0/sum_data_0/i_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/<11>
    -------------------------------------------------  ---------------------------
    Total                                     14.049ns (1.718ns logic, 12.331ns route)
                                                       (12.2% logic, 87.8% route)


Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                11,169 out of  54,576   20%
    Number used as Flip Flops:              11,164
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                5
  Number of Slice LUTs:                     15,960 out of  27,288   58%
    Number used as logic:                   10,220 out of  27,288   37%
      Number using O6 output only:           8,001
      Number using O5 output only:             234
      Number using O5 and O6:                1,985
      Number used as ROM:                        0
    Number used as Memory:                   4,736 out of   6,408   73%
      Number used as Dual Port RAM:          4,216
        Number using O6 output only:         4,152
        Number using O5 output only:             0
        Number using O5 and O6:                 64
      Number used as Single Port RAM:            0
      Number used as Shift Register:           520
        Number using O6 output only:           227
        Number using O5 output only:             1
        Number using O5 and O6:                292
    Number used exclusively as route-thrus:  1,004
      Number with same-slice register load:    981
      Number with same-slice carry load:        22
      Number with other load:                    1


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2 Replies
Registered: ‎02-18-2019

It seems that fifo_generator causes timing error, you could try to enable output registers to relax timing. But you should be careful, because it increases read latency.

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Registered: ‎06-02-2020

I'm not even sure it's possible since the FIFO is part of the FSL. In any case, as you pointed out, the read latency is a problem and I would rather not change anything that may force me into redesigning the logic.

Also, the major part of the delay is routing delay and it all seems to be within the FIFO logic of which I have no control.


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