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Adventurer
Adventurer
10,232 Views
Registered: ‎07-12-2015

There are registers with no clock. Please check your design.

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Hello. I am developing a kind of buffer. Basically, in my application there is a counter variable. When the counter is equal to 0, the application should store user_w_write_8_data into my_buffer and when counter is equal to 1 the application should store my_buffer into din. The problem is that if I generate the bitfile I get the time constraint error:

 

[runtcl 1] ERROR: [Common 17-39] 'send_msg_id' failed due to earlier errors.
[showstopper 1] There are registers with no clock. Please check your design. See Timing Summary Report.

how do I solve this problem?

Here the code:

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity xillydemo is
  port (
     PCIE_PERST_B_LS : IN std_logic;
     PCIE_REFCLK_N : IN std_logic;
     PCIE_REFCLK_P : IN std_logic;
     PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0);
     PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0);
     GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
     PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0);
     PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0));
end xillydemo;

architecture sample_arch of xillydemo is
    signal tmp :  std_logic_vector(7 DOWNTO 0);
  

  component xillybus
    port (
      PCIE_PERST_B_LS : IN std_logic;
      PCIE_REFCLK_N : IN std_logic;
      PCIE_REFCLK_P : IN std_logic;
      PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0);
      PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0);
      GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
      PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0);
      PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0);
      bus_clk : OUT std_logic;
      quiesce : OUT std_logic;
      
      user_r_read_8_rden : OUT std_logic;
      user_r_read_8_empty : IN std_logic;
      user_r_read_8_data : IN std_logic_vector(7 DOWNTO 0);
      user_r_read_8_eof : IN std_logic;
      user_r_read_8_open : OUT std_logic;
      user_w_write_8_wren : OUT std_logic;
      user_w_write_8_full : IN std_logic;
      user_w_write_8_data : OUT std_logic_vector(7 DOWNTO 0);
      user_w_write_8_open : OUT std_logic);
  end component;

  component fifo_8x2048
    port (
      clk: IN std_logic;
      srst: IN std_logic;
      din: IN std_logic_VECTOR(7 downto 0);
      wr_en: IN std_logic;
      rd_en: IN std_logic;
      dout: OUT std_logic_VECTOR(7 downto 0);
      full: OUT std_logic;
      empty: OUT std_logic);
  end component;


-- Synplicity black box declaration
  attribute syn_black_box : boolean;
  attribute syn_black_box of fifo_8x2048: component is true;
  
  signal bus_clk :  std_logic;
  signal quiesce : std_logic;

  signal reset_8 : std_logic;

  signal ram_addr : integer range 0 to 31;
 
  signal user_r_read_8_rden  :  std_logic;
  signal user_r_read_8_empty :  std_logic;
  signal user_r_read_8_data  :  std_logic_vector(7 DOWNTO 0);
  signal user_r_read_8_eof   :  std_logic;
  signal user_r_read_8_open  :  std_logic;
  signal user_w_write_8_wren :  std_logic;
  signal user_w_write_8_full :  std_logic;
  signal user_w_write_8_data :  std_logic_vector(7 DOWNTO 0);
  signal user_w_write_8_open :  std_logic;
  signal wr_en               :  std_logic := '0';
  signal din                 :  std_logic_vector(user_w_write_8_data'range) := (others => '0');

begin
  xillybus_ins : xillybus
    port map (
      -- Ports related to /dev/xillybus_read_8
      -- FPGA to CPU signals:
      user_r_read_8_rden => user_r_read_8_rden,
      user_r_read_8_empty => user_r_read_8_empty,
      user_r_read_8_data => user_r_read_8_data,
      user_r_read_8_eof => user_r_read_8_eof,
      user_r_read_8_open => user_r_read_8_open,

      -- Ports related to /dev/xillybus_write_8
      -- CPU to FPGA signals:
      user_w_write_8_wren => user_w_write_8_wren,
      user_w_write_8_full => user_w_write_8_full,
      user_w_write_8_data => user_w_write_8_data,
      user_w_write_8_open => user_w_write_8_open,

      -- General signals
      PCIE_PERST_B_LS => PCIE_PERST_B_LS,
      PCIE_REFCLK_N => PCIE_REFCLK_N,
      PCIE_REFCLK_P => PCIE_REFCLK_P,
      PCIE_RX_N => PCIE_RX_N,
      PCIE_RX_P => PCIE_RX_P,
      GPIO_LED => GPIO_LED,
      PCIE_TX_N => PCIE_TX_N,
      PCIE_TX_P => PCIE_TX_P,
      bus_clk => bus_clk,
      quiesce => quiesce
   );

  process (bus_clk)
  
  variable counter : integer := 0; 
  variable my_buffer     :  std_logic_vector(7 downto 0) := (others => '0');
  
  begin 
    wr_en <= user_w_write_8_wren;
    din <= user_w_write_8_data;
    user_r_read_8_eof <= user_r_read_8_empty and not(user_w_write_8_open);
    
    if (counter = 1) then 
        din <= my_buffer;
        counter := 0;
    else
        my_buffer := user_w_write_8_data;
        counter := 1;
    end if;
            
            
    
  end process;

--  8-bit loopback

  fifo_8 : fifo_8x2048
    port map(
          clk        => bus_clk,
          srst       => reset_8,
          din        => din,
          wr_en      => wr_en,
          rd_en      => user_r_read_8_rden,
          dout       => user_r_read_8_data,
          full       => user_w_write_8_full,
          empty      => user_r_read_8_empty
      );

    reset_8 <= not (user_w_write_8_open or user_r_read_8_open);

    --user_r_read_8_eof <= '0';
    
end sample_arch;
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1 Solution

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Highlighted
Professor
Professor
18,983 Views
Registered: ‎08-14-2007

Re: There are registers with no clock. Please check your design.

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In your process, you have a sensitivity list consisting of just bus_clk, but no edge dependency.  Typically you want to use the clock as a rising edge trigger like:

 

  process (bus_clk)
 
  variable counter : integer := 0;
  variable my_buffer     :  std_logic_vector(7 downto 0) := (others => '0');
 
  begin
    if rising_edge (bus_clk) then
      wr_en <= user_w_write_8_wren;
      din <= user_w_write_8_data;
      user_r_read_8_eof <= user_r_read_8_empty and not(user_w_write_8_open);
      
      if (counter = 1) then
          din <= my_buffer;
          counter := 0;
      else
          my_buffer := user_w_write_8_data;
          counter := 1;
      end if;
    end if;
  end process;

 

As written, the process will run on both clock edges for simulation, but for synthesis the sensitivity list will be ignored, so it becomes totally combinatorial.

-- Gabor

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6 Replies
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Xilinx Employee
Xilinx Employee
10,225 Views
Registered: ‎09-20-2012

Re: There are registers with no clock. Please check your design.

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Hi @junior_hpc

 

Is this an error? Is the bit file not generated?

 

You can open implemented design and use check_timing command to find out if there are any registers in the design whose clocks does not have create_clock constraints.

 

Thanks,

Deepika. 

Thanks,
Deepika.
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Highlighted
Moderator
Moderator
10,207 Views
Registered: ‎07-01-2015

Re: There are registers with no clock. Please check your design.

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Hi @junior_hpc,

 

Please run report_timing_summary in Tcl console to get more clarifications about number of registers/latches with no_clock.

 

Thanks,
Arpan

Thanks,
Arpan
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Highlighted
Professor
Professor
18,984 Views
Registered: ‎08-14-2007

Re: There are registers with no clock. Please check your design.

Jump to solution

In your process, you have a sensitivity list consisting of just bus_clk, but no edge dependency.  Typically you want to use the clock as a rising edge trigger like:

 

  process (bus_clk)
 
  variable counter : integer := 0;
  variable my_buffer     :  std_logic_vector(7 downto 0) := (others => '0');
 
  begin
    if rising_edge (bus_clk) then
      wr_en <= user_w_write_8_wren;
      din <= user_w_write_8_data;
      user_r_read_8_eof <= user_r_read_8_empty and not(user_w_write_8_open);
      
      if (counter = 1) then
          din <= my_buffer;
          counter := 0;
      else
          my_buffer := user_w_write_8_data;
          counter := 1;
      end if;
    end if;
  end process;

 

As written, the process will run on both clock edges for simulation, but for synthesis the sensitivity list will be ignored, so it becomes totally combinatorial.

-- Gabor

View solution in original post

Highlighted
Voyager
Voyager
10,161 Views
Registered: ‎04-21-2014

Re: There are registers with no clock. Please check your design.

Jump to solution

What Gabor said. 

 

Also, VHDL training (or a good text on VHDL for synthesis) would help in the long run.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Highlighted
Explorer
Explorer
10,133 Views
Registered: ‎04-28-2015

Re: There are registers with no clock. Please check your design.

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Hi @junior_hpc,

Please change your code according to Gabor's suggestion and let us know if the issue is resolved.
If yes, please close this thread by marking the reply that helped you as 'solution'.
This will help others in the long run.

Thanks,
Tushar.
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Highlighted
Adventurer
Adventurer
10,125 Views
Registered: ‎06-10-2014

Re: There are registers with no clock. Please check your design.

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Hi,

 

Just a closing remark: This error was generated by a script named showstopper.tcl, which checks the timing report for issues that are worth paying attention to. If such are found, it produces an error and prevents the generation of a bitfile.

 

The intention of this script, which is part of demo projects for Xillybus, is to draw the designer's attention to a timing related problem (registers without clock in this case). We should all check the timing report after each implementation, but in practice, if there's a bitfile ready to go, it's easy to overlook this. Not with the script.

 

It's of course possible to turn the script off in the implementation settings (it's a tcl.pre script for write_bitstream).

 

Regards,

   Eli