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Participant
Participant
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Registered: ‎06-04-2020

There is large inter clock skew causing hold violations

TIMING #43 Warning There is a large inter-clock skew of 5.440 ns between U_top/core/tile/_T_23_reg/C (clocked by FOUTPOSTDIV_clk_wiz_0) and U_top/core/tile/core/csr/_T_42_reg[33]/R (clocked by FOUTPOSTDIV_clk_wiz_0) that results in large hold timing violation(s) of -4.859 ns. Fixing large hold violations during routing might impact setup slack and result in more difficult timing closure

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Teacher
Teacher
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Registered: ‎07-09-2009

Whats the question ?
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Scholar
Scholar
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Registered: ‎08-07-2014

@Harish_Algat ,

1. More details regarding the failing path are required.

2. An understanding about the failing path is also required.

Please do not make it appear like your comment in the previous post - https://forums.xilinx.com/t5/Timing-Analysis/Setup-Violation/m-p/1177595#M20303

 

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