UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor 1315chw
Visitor
753 Views
Registered: ‎12-26-2018

[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

Jump to solution

1545815724(1).png1545815652(1).png1545815684(1).png

 

Tags (1)
0 Kudos
1 Solution

Accepted Solutions
Voyager
Voyager
671 Views
Registered: ‎02-01-2013

Re: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

Jump to solution

This is an inter-clock timing violation. Are you sure it's a valid path that needs to be timed? Generally, data exchanged between clock domains pass through a mechanism (e.g., a FIFO) that allows data to be transferred safely, regardless of the timing relationship between the clocks. In such a case, that inter-clock timing path needs to be marked as a False Path, so the tool doesn't waste time trying to meet timing.

-Joe G.

 

0 Kudos
4 Replies
Teacher xilinxacct
Teacher
680 Views
Registered: ‎10-23-2018

Re: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

Jump to solution

@1315chw

Can you reduce the clock speed and get it to operated successfully?

0 Kudos
Voyager
Voyager
672 Views
Registered: ‎02-01-2013

Re: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

Jump to solution

This is an inter-clock timing violation. Are you sure it's a valid path that needs to be timed? Generally, data exchanged between clock domains pass through a mechanism (e.g., a FIFO) that allows data to be transferred safely, regardless of the timing relationship between the clocks. In such a case, that inter-clock timing path needs to be marked as a False Path, so the tool doesn't waste time trying to meet timing.

-Joe G.

 

0 Kudos
Visitor 1315chw
Visitor
651 Views
Registered: ‎12-26-2018

Re: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

Jump to solution

Yes,I copied the xdc templetes of the ip core to my xdc file,and it works!But I have a new problem with generating bitstream.It's[DRC23-20]

drc_problem.png
0 Kudos
Visitor 1315chw
Visitor
646 Views
Registered: ‎12-26-2018

Re: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

Jump to solution

I just copied the templetes to my xdc file,and it works!Thank you for your reply.

Regards,William

0 Kudos