Timing Analysis Resources

[yashp]

Timing Analysis forum is the open platform to discuss about the Static timing analysis, methodology for better use cases and constraints related queries.

If you can’t find your answer in the below existing documentation, please always feel free to post your question on this Forum’s page.

User Guides: Xilinx technical documents intended for better performance and understanding.

Vivado:

UG 949: Ultrafast Design Methodology User Guide (link)

UG 906: Design Analysis and Closure

UG 903: Vivado Using Constraints

UG 835: Vivado TCL Commands

ISE:

UG 612: Timing closure user guide

UG 625:  Xilinx constraint guide

Video Tutorials: Xilinx graphical demonstration for ease of use approach specific to the application. (Video Links)

Answer Records: Xilinx answer records are public accessible documents specific to use cases or issues. You can search this AR’s on Xilinx website. (Search Here)  

Solution Center: ISE_solution_center

Known Issues: Vivado_known_issues

[bala2016]

Dear Yash,

I implemented a 32-bit adder by targeting a Kintex-7 FPGA by making use of the fast carry logic inherent in the FPGA. a31 to a0, and b31 to b0 are the inputs, and s32 to s0 are the sum outputs. I have attached the Verilog code and the post-place and route static timing report. May I know how to determine the minimum clock period from this report? BTW, does the clock to destination pad delay given in the second table refers to the combinational path delays for the different sum outputs? I would greatly appreciate your early reply.

Thanks in advance,

Bala

[ebrahim_nouri]

In this report it is mentioned that you have not used any timing constraint file in your project. first you have to have a  UCF (user constraint file) and try to implement your design again, by then the ISE will give you timing report and timing slack and the maximum frequency of your design.