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Visitor
Visitor
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Registered: ‎03-07-2018

Timing Constraints Help

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I'm trying to write timing constraints for an External Interface Memory (EIM) from an ARM device to an FPGA. The EIM signals work a lot like a spi interface. The full timing requirement table is attached below with the timing diagram but all the input signals have one timing requirement min/max and all the output signals have another.

 

The clock period I'm using is 22ns. Using the table and timing diagrams attached, I sketched what the input signals should look like in Figure 9 and created the following constraint:

 

 

set_input_delay -clock [get_clocks EIM_BCLK] -min  10 [get_ports {EIM_ADDRxx[*]}]
set_input_delay -clock [get_clocks EIM_BCLK] -max 13 [get_ports {EIM_ADDRxx[*]}]

 

Does the above code snippet correct for a signal like Figure 9? 

 

In addition, what do the output delays look like for Figure 11 where WE18 and WE19 are 2ns each? This is data going out of the FPGA an into the processor. I have the following:

 

set_output_delay -clock [get_clocks EIM_BCLK] -min  -2 [get_ports {EIM_DATA[*]}]
set_output_delay -clock [get_clocks EIM_BCLK] -max 2 [get_ports {EIM_DATA[*]}]

 

Are these constraints correct? Thank you for any help

 

 

Fig950.png
OutputData50.png
TimingAndTable50.png
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Mentor
Mentor
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Registered: ‎06-16-2013

Re: Timing Constraints Help

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Hi @katkinson

 

I think that your setting is almost correct.

You can go ahead.

 

Best regards,

View solution in original post

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Mentor
Mentor
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Registered: ‎06-16-2013

Re: Timing Constraints Help

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Hi @katkinson

 

I think that your setting is almost correct.

You can go ahead.

 

Best regards,

View solution in original post

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