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Participant
Participant
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Registered: ‎06-04-2020

Timing Constraints

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Hello, clock generated by MMCM will fall in which group synchronous group or asynchronous group?

I have a MMCM which produces 3 clocks of different frequencies, but I have timing violations on inter clock groups and intra clock groups. In inter clock groups the violations are on output clocks of MMCM can I make them into asynchronous group.

 

 

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Xilinx Employee
Xilinx Employee
362 Views
Registered: ‎05-14-2008

You can make them asynchronous groups by constraints only when they are indeed asynchronous or the CDC paths timing between them is guaranteed so do not need timing analysis.

However, clocks generated from the same MMCM are synchronous as their phase relationships are known. Why do you want to set them asynchronous?

As for the timing errors in the inter clock paths, you need to analyze why they are failing timing? Then determine how to resolve those violations.

-vivian

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Moderator
Moderator
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Registered: ‎11-04-2010

After making these clock groups as asynchronous clocks, you have to use logic to promise correction of the data path crossing these clock groups. (Ex: Handshaking, Asynch FIFO...)

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Participant
Participant
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Registered: ‎06-04-2020
you meant so say I have to make design changes as well?
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Moderator
Moderator
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Registered: ‎11-04-2010

If you don't have any logic for crossing clock domains, you have to change your source code.

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Xilinx Employee
Xilinx Employee
363 Views
Registered: ‎05-14-2008

You can make them asynchronous groups by constraints only when they are indeed asynchronous or the CDC paths timing between them is guaranteed so do not need timing analysis.

However, clocks generated from the same MMCM are synchronous as their phase relationships are known. Why do you want to set them asynchronous?

As for the timing errors in the inter clock paths, you need to analyze why they are failing timing? Then determine how to resolve those violations.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------

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Participant
Participant
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Registered: ‎06-04-2020
I have generated the timing constraints with the help of tool and after synthesis timing report there are no setup violations (Hold Violations are there) but after Implementation I have both setup and hold violations.
Can you guide me more on how to resolve timing failed paths

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Xilinx Employee
Xilinx Employee
331 Views
Registered: ‎05-14-2008

UG906 gives basic knowledge of timing analysis.

UG949 gives common causes to timing violation and corresponding solutions.

-vivian

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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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