09-16-2010 12:43 PM
I ran into timing closure issues as I tried to migrate a xc3sd1800a design to the xc3sd3400a core through the EDK design flow. The design would fit within a xc3sd1800a and achieve timing closure. With the same speed grade but over the xc3sd3400a core (same package but with more resources, the only reason I’m migrating is because I can’t find the industrial grade version of the xc3sd1800a) I cannot pass the port-PAR timing verifications anymore.
So basically my first question is, for a given design which I know will fit within a smaller FPGA would it make more sense (strictly with respect to timing closure), to use a smaller FPGA? Or did I just ran into a XST/PAR non-sense? I would have though that as the resources become more available, the PAR tool would have more liberty to properly work and achieve timing closure.
Speaking of non-sense, I tried to generate a bitstream for the same design but through the ISE flow this time (ISE project simply implementing the EDK project). Weird thing is that it went through just fine. It easily passed the timing constraint. As far as I can see there are no additional PAR or XST options through ISE which would explain this.
Anybody has an explanation?
09-16-2010 04:52 PM
It's not always true that more available resources in FPGA necessarily lead to better timing. I've seen exactly the opposite many times.
One methodology you can use to improve timing is to floorplan your design. It can be done from the PlanAhead or manually using AREA_GROUP UCF constraints.
There is no fundamental difference between ISE and EDK flows. Both use the same tools underneath: xst (or other synthesis tool), ngdbuild, map,par, etc. So the differences you're seeing might be because somehow ISE and EDK flows use different parameters to xst, or other tools. You might want to compare the logs from both flows.