04-23-2018 10:11 AM
I am new to the timing analysis and have a problem for the post-implementation timing simulation as figure below. fbclkp and fclkp are pair of LVDS clock signal get from CLK. Txp and Txn data are LVDS data signal generated from my design that is sent to AD9361 for further processing. It can be observed that the rising edge and falling edge of fbclk overlap with the a region that is unstable for txp and txn. May I ask that how to solve this kind of timing problem?
04-23-2018 10:41 AM
First, this isn't a "timing" problem, this is either not a problem, or a design problem.
When you interface to an external device, you need an architecture that can meet the timing requirements of that external device. Different devices need different timing requirements.
Some devices are perfectly happy with timing that looks like this - this would be an "Edge aligned source synchronous DDR interface".
Other devices need other clock/data timing relationships - the other most common one is "Center aligned source synchronous DDR interface".
You need to determine which yours is.
If you need a center aligned interface, then you need to design a clocking architecture that meets those needs. Most often the way to do it is:
- input clock comes in on clock capable input, through an input buffer (IBUF or IBUFG)
- output of IBUF goes to input of MMCM
- MMCM generates two clocks - CLKOUT0 with a 0 degree phase shift, CLKOUT1 with a 90 degree phase shift
- both output clocks go to BUFGs
- in UltraScale/UltraScale+ the two clocks are placed in the same CLOCK_DELAY_GROUP (with properties)
- the 90 degree clock (after BUFG) drives an ODDR or OSERDES to generate the forwarded clock (fixed 0101 pattern)
- the 0 degree clock (after BUFG) drives all data generation and ultimately the ODDR/OSERDES that sends data
You should also have appropriate timing constraints (create_generated_clock on forwarded clock and set_output_delay on forwarded data) to ensure that the design meets the needs of the external device.