12-14-2016 11:57 PM
hi all , I am working on Xilinx 7020 customized board. I did implementation of my design when I got the timing summary report, it shows that timing constraint are not met. how can I design my design to meet all timing constraints. and now how can I solve these timing problems. I have attached my timing summary report please someone help me to solve these problems.
12-15-2016 12:38 AM
12-15-2016 12:38 AM
From the snapshot your WNS is -98ns which is impossible to meet. This is clear indication of under constraining your design.
Before doing any modification, my 1st suggestion would be to check constraints. Looks like there are few unrealistic requirement in CDC paths those might be asynchronous, or need some exceptions.
Also there are 111 timing check messages, revisit them and see what constraints are missing.
In Vivado all clocks are synchronous, user have to write exceptions if any clock to clock domain is asynchronous.
Also just from snapshot, I cannot provide any further info. Please share your timing report of implemented design.
Then I can provide few more suggestions about constraints.
NOTE: Use UG903 and UG906 for better understanding of timing.
12-15-2016 07:13 AM
Agree with @yashp - it's worth reviewing your constraints to make sure you don't have any incorrect clock crossing paths timed.
However, this is not the root of the problem. Even if the clock crossing constraints are incorrect, the worst this can do is end up with a path requirement of 0. To have a TNS of -98, that means that your data path is at least 98ns in length. So, unless your clock rates are around 10MHz, there is not even the slightest chance of getting this to work.
Most likely, this is a failure in architecture. In RTL it is really easy to write a complete algorithm as if it were a C algorithm - and even get that algorithm to give correct results. However, if while the code was written the writer didn't think hardware then what you have is nothing more than an algorithm.
In order to implement hardware you need an architecture - you need to plan out what operations need to happen, roughly how long they are going to take, how often they are going to be used, how many copies of them you need and what pipelining is going to be done in order map the algorithm into an architecture.
If you don't do this, and simply write and synthesize your algorithm, you end up with a non-viable architecture - one that fails timing not by a little, but by a huge amount (which it looks like could be the case here).
So, yes, showing the failing path will help us confirm (or maybe deny) this assumption - but if this is the case, you will need to go back to the drawing board and design an architecture to do what you need.
12-15-2016 11:34 PM