01-20-2019 11:40 AM
I am having a problem following the recommendations in The product guide for the AXI Quad SPI core V3.2 (PG153). The project targets an Artix 7, and I'm using vivado 2018.3; I'm trying to use the constraints recommended on pages 89-90 of PG153.
The application is to be able to reprogram the configuration Flash memory device. I am using the same pins as are used for configuration, and the STARTUPE2 primitive (internal to the IP core) is used to access the CCLK pin via the USRCCLK0 pin.
The recommended constraints don't seem to create the generated clock "clk_sck". I get an error message "[Vivado 12-508] No pins matched '*USRCCLKO'. ["C:/xilinxdesigns/andromeda/andromeda.srcs/constrs_1/new/timingconstraints.xdc":151]"
followed by 6 error messages "[Vivado 12-646] clock 'clk_sck' not found. ["C:/xilinxdesigns/andromeda/andromeda.srcs/constrs_1/new/timingconstraints.xdc":155]"
The problem seems to be: create_generated_clock fails because it doesn't recognise pin USRCCLK0. That would be internal to the IP - it isn't presented to the user. How do I get vivado to recognise it please?
The constraints are in my top level timingconstraints.xdc file - these are the relevant ones (the formulas seemed to get replaced by the calculated values by the timing wizard, but I don't think the meaning has been affected - and this still failed before I ran the timing wizard):
01-24-2019 08:36 AM
I have a similar problem by using AXI Quad SPI core, (STARTUPE disabled).
Using the template constrain file from the IP core and the fowling line fails:
01-24-2019 11:32 AM - edited 01-25-2019 04:01 AM
If you have disabled STARTUPE2, you should wire the core to the spi output clock pin yourself. My IO pins are done with ports on the IP integrator block diagram and pin numbers allocated in the elaborated design. If that pin is called "SPI_CLOCK_OUT" on your block diagram, the constraint would be:
I should add: if you have disabled STARTUPE2, then it is a different issue form the one I'm having.