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Observer laurencebarker
Observer
215 Views
Registered: ‎05-27-2018

Timing constraints for AXI Quad SPI core using STARTUPE2

I am having a problem following the recommendations in The product guide for the AXI Quad SPI core V3.2 (PG153). The project targets an Artix 7, and I'm using vivado 2018.3; I'm trying to use the constraints recommended on pages 89-90 of PG153.

The application is to be able to reprogram the configuration Flash memory device. I am using the same pins as are used for configuration, and the STARTUPE2 primitive (internal to the IP core) is used to access the CCLK pin via the USRCCLK0 pin.

The recommended constraints don't seem to create the generated clock "clk_sck". I get an error message "[Vivado 12-508] No pins matched '*USRCCLKO'. ["C:/xilinxdesigns/andromeda/andromeda.srcs/constrs_1/new/timingconstraints.xdc":151]"

followed by 6 error messages "[Vivado 12-646] clock 'clk_sck' not found. ["C:/xilinxdesigns/andromeda/andromeda.srcs/constrs_1/new/timingconstraints.xdc":155]"

 

The problem seems to be: create_generated_clock fails because it doesn't recognise pin USRCCLK0. That would be internal to the IP - it isn't presented to the user. How do I get vivado to recognise it please?

 

The constraints are in my top level timingconstraints.xdc file - these are the relevant ones (the formulas seemed to get replaced by the calculated values by the timing wizard, but I don't think the meaning has been affected - and this still failed before I ran the timing wizard):

# serial prom constraints: see Xilinx PG153 p89-90
# You must provide all the delay numbers
# CCLK delay is 0.5, 8 ns min/max for Artix7-2; refer Data sheet
# Consider the max delay for worst case analysis
# Following are the SPI device parameters
# Max Tco
# Min Tco
# Setup time requirement
# Hold time requirement
# Following are the board/trace delay numbers
# Assumption is 2" to 4"
### End of user provided delay numbers
# this is to ensure min routing delay from SCK generation to STARTUP input
# User should change this value based on the results
# having more delay on this net reduces the Fmax
set_max_delay -datapath_only -from [get_pins -hier *SCK_O_reg_reg/C] -to [get_pins -hier *USRCCLKO] 2.000
set_min_delay -from [get_pins -hier *SCK_O_reg_reg/C] -to [get_pins -hier *USRCCLKO] 0.100
# Following command creates a divide by 8 clock
# It also takes into account the delay added by STARTUP block to route the CCLK
create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_0/ext_spi_clk] [get_pins -hierarchical *USRCCLKO] -edges {1 9 17} -edge_shift [list 8.000 8.000 8.000]
# Data is captured into FPGA on the second rising edge of ext_spi_clk after the SCK falling edge
# Data is driven by the FPGA on every alternate rising_edge of ext_spi_clk
set_input_delay -clock clk_sck -max 8.800 [get_ports PROM_SPI_MISO] -clock_fall
set_input_delay -clock clk_sck -min 0.400 [get_ports PROM_SPI_MISO] -clock_fall
set_multicycle_path 2 -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]
set_multicycle_path 1 -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]
# Data is captured into SPI on the following rising edge of SCK
# Data is driven by the IP on alternate rising_edge of the ext_spi_clk
set_output_delay -clock clk_sck -max 1.700 [get_ports PROM_SPI_MOSI]
set_output_delay -clock clk_sck -min -2.200 [get_ports PROM_SPI_MOSI]
set_output_delay -clock clk_sck -max 1.700 [get_ports PROM_SPI_SSn[0]]
set_output_delay -clock clk_sck -min -2.200 [get_ports PROM_SPI_SSn[0]]
set_multicycle_path 2 -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck
set_multicycle_path 1 -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck
 
 
 
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2 Replies
146 Views
Registered: ‎07-04-2017

Re: Timing constraints for AXI Quad SPI core using STARTUPE2

I have a similar problem by using AXI Quad SPI core, (STARTUPE disabled).

Using the template constrain file from the IP core and the fowling line fails: 

create_generated_clock -name clk_sck -source [get_pins -hierarchical
*axi_quad_spi_1/ext_spi_clk] [get_ports <SCK_IO>] -edges {3 5 7}
 
get_ports <SCK_IO> fails, because it doesn't recognise port SCK_IO.....
 
I have tried other commands like get_pins, and other names of the spi output clock. it doesn't work. somehow, I can't get the right name of the spi output clock
 
best regards
 
 

 

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Observer laurencebarker
Observer
131 Views
Registered: ‎05-27-2018

Re: Timing constraints for AXI Quad SPI core using STARTUPE2

If you have disabled STARTUPE2, you should wire the core to the spi output clock pin yourself. My IO pins are done with ports on the IP integrator block diagram and pin numbers allocated in the elaborated design. If that pin is called "SPI_CLOCK_OUT" on your block diagram, the constraint would be:

create_generated_clock -name clk_sck -source [get_pins -hierarchical
*axi_quad_spi_1/ext_spi_clk] [get_ports {SPI_CLOCK_OUT}] -edges {3 5 7}
 
Do you have 2 SPI cores - if not, the name of your core instance might actually be axi_quad_spi_0. Mine was!
 
(I have no idea if the {} brackets are important; some constraints have them, some don't and both seem to work)

 

 

I should add: if you have disabled STARTUPE2, then it is a different issue form the one I'm having.

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