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Adventurer
Adventurer
431 Views
Registered: ‎10-29-2017

Timing failed in Interlaken IP

Hi,

   I need to test Interlaken IP with the board. so, I configured IP (with OOBFC) and generated example design of that. I have declared input reference clock to FPGA and init_clk,gt_ref_clk, rx_fc_clk to IP. I didn't do any changes in the example design. 

   After implementation is done, I found Negative slack issues with timing. These issues are found only in inter-clock path (setup and hold) and async_default path. As these paths are internal to the design, I don't know how to solve this issue.  

   Will bitstream with failed timings create any issue when we work with board? or as it is an example design, can we use the same Image file, will that work properly? 

   Please guide me. 

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3 Replies
Scholar drjohnsmith
Scholar
413 Views
Registered: ‎07-09-2009

Re: Timing failed in Interlaken IP

if u cant meet timing, and u are certain its not in your design, u need a faster chip.

what chip / speed / board u trying to target at what interlarken speed,

are u certain your part that feeds / reads the interlarken ip is not the cause ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Adventurer
Adventurer
412 Views
Registered: ‎10-29-2017

Re: Timing failed in Interlaken IP

Hi,

   Device is XCVU9P-FSGD2104-2-e.

   Interlaken line Rate 25.78125 Gbps with 4 lanes.

   GTY Refclk freq is 402.8320313 MHz and Init clk freq is 250 MHz.

   ILKN Core is X0Y0. 

   Not yet tried with board and find timing issues at the time of bitstream generation.

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Adventurer
Adventurer
357 Views
Registered: ‎10-29-2017

Re: Timing failed in Interlaken IP

Hi,

   https://forums.xilinx.com/t5/Welcome-Join/Total-Negative-Slack-vs-Worst-Negative-Slack/td-p/308077

I went through the above link and found that TNS cannot be negative. It is mentioned in 'accepted as a solution' post. 

  In this Interlaken IP, i got TNS with negative -431.982. I just gave the constraint file(unable to attach) as mentioned below.  

  Please check and help me where I'm wrong and what to do further?

##CONSTRAINT_FILE : Interlaken.xdc

set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets IBUFDS_inst_2/O]
#set_max_delay -datapath_only -from [get_pins [list {i_rx_oobfc/i_CORE/i_ACK/eventout_reg[0]/C} {i_rx_oobfc/i_CORE/i_ACK/eventout_reg[1]/C} {i_rx_oobfc/i_CORE/i_ACK/eventout_reg[2]/C} {i_rx_oobfc/i_CORE/i_ACK/eventout_reg[3]/C}]] -to [get_pins [list {i_rx_oobfc/i_CORE/i_REQ/i_SYNCER/meta_reg[0]/D} {i_rx_oobfc/i_CORE/i_REQ/i_SYNCER/meta_reg[1]/D} {i_rx_oobfc/i_CORE/i_REQ/i_SYNCER/meta_reg[2]/D} {i_rx_oobfc/i_CORE/i_REQ/i_SYNCER/meta_reg[3]/D} {i_rx_oobfc/i_CORE/i_REQ/i_SYNCER/meta_reg[4]/D}]] 10.000
#set_false_path -to [get_pins [list {i_rx_oobfc/i_CORE/i_ACK/i_SYNCER/meta_reg[0]/D} {i_rx_oobfc/i_CORE/i_ACK/i_SYNCER/meta_reg[1]/D} {i_rx_oobfc/i_CORE/i_ACK/i_SYNCER/meta_reg[2]/D} {i_rx_oobfc/i_CORE/i_ACK/i_SYNCER/meta_reg[3]/D} {i_rx_oobfc/i_CORE/i_OVF/i_SYNCER/meta_reg[0]/D} {i_rx_oobfc/i_CORE/i_REQ/i_SYNCER/meta_reg[0]/D} {i_rx_oobfc/i_CORE/i_REQ/i_SYNCER/meta_reg[1]/D} {i_rx_oobfc/i_CORE/i_REQ/i_SYNCER/meta_reg[2]/D} {i_rx_oobfc/i_CORE/i_REQ/i_SYNCER/meta_reg[3]/D} {i_rx_oobfc/i_CORE/i_REQ/i_SYNCER/meta_reg[4]/D}]]
#------------------------------------------------------------------------------
# (c) Copyright 2013 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#------------------------------------------------------------------------------


#------------------------------------------------------------------------------
# Interlaken example design-level XDC file
# ----------------------------------------------------------------------------------------------------------------------
set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets rx_fc_clk_IBUF_inst/O]

set_input_delay -clock sys_clk_p 5000.000 [get_ports sys_reset]

set_property IOSTANDARD DIFF_SSTL15 [get_ports gt_ref_clk0_n]
set_property IOSTANDARD DIFF_SSTL15 [get_ports gt_ref_clk0_p]

###Constraints to fix the ILKN core Location
set_property LOC ILKNE4_X0Y0 [get_cells DUT/inst/i_ilkn_top_inst/ilkn_inst]

 

 

set_property PHASESHIFT_MODE WAVEFORM [get_cells i_rx_oobfc/i_RX_OOBFC_MMCME3_ADV]

 

 


### OOBFC Constraints start

set_false_path -fall_from [get_clocks -of_objects [get_pins i_CLK_GEN/inst/mmcme4_adv_inst/CLKOUT2]] -to [get_clocks TX_FC_CLK]
###---MMCM multicycple path constraints---

 

 

 

### OOBFC Constraints end

### OOBFC Constraints starts
set_false_path -from [get_pins i_tx_oobfc/i_CORE/i_ODDR_SYNC/CLKDIV] -to [get_ports tx_fc_sync];
set_false_path -from [get_pins i_tx_oobfc/i_CORE/i_ODDRE1_DATA/CLKDIV] -to [get_ports tx_fc_data];

### Ignore timing path to "PRESET" pins of the synchronizer chain

### Ignore Syncer path

###Ignore RAMA to async FF ram_rdata_int_reg[]

### Ignore eventout_reg[] through RAMA to async FF ram_rdata_int_reg[]
### OOBFC Constraints end

 


### These are sample constraints, please use correct constraints for your device
### As per GT recommendation, ref_clk should be connected to the middle quad.

### User needs to uncomment the below line and based on ILKN core location and GT group selected, change the gt_ref_clk pin location accordingly.
#set_property PACKAGE_PIN AC9 [get_ports gt_ref_clk0_p]


### For init_clk input pin assignment, If single ended clock is not available on board, user has to instantiate IBUFDS to covert differential clock to
### single ended clock and make the necessary changes for the clock mapping.
### Change these IO Loc XDC constraints as per your board and device
#set_property PACKAGE_PIN AM12 [get_ports init_clk]
#set_property PACKAGE_PIN AG12 [get_ports sys_reset]
#set_property PACKAGE_PIN AJ14 [get_ports lbus_tx_rx_restart_in]
#set_property LOC AR12 [get_ports tx_done_led]
#set_property LOC AR13 [get_ports tx_busy_led]
#set_property LOC AM9 [get_ports tx_fail_led]
#set_property LOC AN8 [get_ports rx_gt_locked_led]
#set_property LOC AP8 [get_ports rx_aligned_led]
#set_property LOC AP10 [get_ports rx_done_led]
#set_property LOC AR10 [get_ports rx_failed_led]
#set_property LOC AR11 [get_ports rx_busy_led]

 

### Push Buttons
set_property IOSTANDARD LVCMOS18 [get_ports sys_reset]

### Output as LEDs
set_property IOSTANDARD LVCMOS18 [get_ports tx_done_led]
##
##
set_property IOSTANDARD LVCMOS18 [get_ports tx_fail_led]
##
##
##
set_property IOSTANDARD LVCMOS18 [get_ports rx_done_led]
##
set_property IOSTANDARD LVCMOS18 [get_ports rx_failed_led]
##


set_property PACKAGE_PIN BC45 [get_ports gt0_rxp_in]
set_property PACKAGE_PIN BA45 [get_ports gt1_rxp_in]
set_property PACKAGE_PIN AW45 [get_ports gt2_rxp_in]
set_property PACKAGE_PIN AV43 [get_ports gt3_rxp_in]
set_property PACKAGE_PIN AL36 [get_ports gt_ref_clk0_p]
set_property PACKAGE_PIN AW20 [get_ports tx_fc_clk]
set_property PACKAGE_PIN BE17 [get_ports rx_fc_clk]
set_property PACKAGE_PIN AW21 [get_ports F1_SYS_300_REF_CLK1_P]
set_property PACKAGE_PIN AV22 [get_ports init_clk_p]
set_property PACKAGE_PIN BC18 [get_ports tx_fc_sync]
set_property PACKAGE_PIN BB21 [get_ports rx_fc_data]
set_property PACKAGE_PIN BC21 [get_ports rx_fc_sync]
set_property PACKAGE_PIN BA19 [get_ports tx_fc_data]
set_property PACKAGE_PIN AL21 [get_ports sys_reset]
set_property PACKAGE_PIN AN21 [get_ports rx_done_led]
set_property PACKAGE_PIN AN22 [get_ports tx_done_led]
set_property PACKAGE_PIN AM21 [get_ports tx_fail_led]
set_property PACKAGE_PIN AP20 [get_ports rx_failed_led]
set_property IOSTANDARD LVCMOS12 [get_ports EMCCLK]
set_property PACKAGE_PIN AM26 [get_ports EMCCLK]
set_property PACKAGE_PIN AL20 [get_ports FPGA_CMC_GPIO0]
set_property PACKAGE_PIN BC19 [get_ports FPGA_CMC_GPIO1]
set_property PACKAGE_PIN BD18 [get_ports FPGA_CMC_GPIO2]
set_property PACKAGE_PIN BF18 [get_ports FPGA_CMC_GPIO3]
set_property PACKAGE_PIN AU21 [get_ports FPGA_ZYNQ_GPIO1]
set_property PACKAGE_PIN AU20 [get_ports FPGA_ZYNQ_GPIO0]
set_property PACKAGE_PIN AR22 [get_ports FPGA_ZYNQ_GPIO2]
set_property PACKAGE_PIN AR21 [get_ports FPGA_ZYNQ_GPIO3]
set_property PACKAGE_PIN AL25 [get_ports {F1_QSPI1_DQ[0]}]
set_property PACKAGE_PIN AM25 [get_ports {F1_QSPI1_DQ[1]}]
set_property PACKAGE_PIN AP23 [get_ports {F1_QSPI1_DQ[2]}]
set_property PACKAGE_PIN AP24 [get_ports {F1_QSPI1_DQ[3]}]


set_property PACKAGE_PIN BD23 [get_ports nF1_QSP2_CS]

set_property IOSTANDARD LVDS [get_ports F1_SYS_300_REF_CLK1_P]
set_property IOSTANDARD LVCMOS18 [get_ports FPGA_CMC_GPIO0]
set_property IOSTANDARD LVCMOS18 [get_ports FPGA_CMC_GPIO1]
set_property IOSTANDARD LVCMOS18 [get_ports FPGA_CMC_GPIO2]
set_property IOSTANDARD LVCMOS18 [get_ports FPGA_CMC_GPIO3]
set_property IOSTANDARD LVCMOS18 [get_ports FPGA_ZYNQ_GPIO0]
set_property IOSTANDARD LVCMOS18 [get_ports FPGA_ZYNQ_GPIO1]
set_property IOSTANDARD LVCMOS18 [get_ports FPGA_ZYNQ_GPIO2]
set_property IOSTANDARD LVCMOS18 [get_ports FPGA_ZYNQ_GPIO3]
set_property IOSTANDARD LVCMOS12 [get_ports {F1_QSPI1_DQ[3]}]
set_property IOSTANDARD LVCMOS12 [get_ports {F1_QSPI1_DQ[2]}]
set_property IOSTANDARD LVCMOS12 [get_ports {F1_QSPI1_DQ[1]}]
set_property IOSTANDARD LVCMOS12 [get_ports {F1_QSPI1_DQ[0]}]
set_property IOSTANDARD LVDS [get_ports init_clk_p]
set_property IOSTANDARD LVCMOS12 [get_ports nF1_QSP2_CS]
set_property IOSTANDARD LVCMOS18 [get_ports rx_fc_clk]
set_property IOSTANDARD LVCMOS18 [get_ports rx_fc_data]
set_property IOSTANDARD LVCMOS18 [get_ports rx_fc_sync]
set_property IOSTANDARD LVCMOS18 [get_ports tx_fc_clk]
set_property IOSTANDARD LVCMOS18 [get_ports tx_fc_data]
set_property IOSTANDARD LVCMOS18 [get_ports tx_fc_sync]


set_false_path -from [get_ports sys_reset]
create_clock -period 2.482 [get_ports gt_ref_clk0_p]
set_false_path -to [get_pins DUT/inst/i_ilkn_top_inst/*/CTL_RX_FORCE_RESYNC]
set_false_path -to [get_pins DUT/inst/i_ilkn_top_inst/*/CTL_TX_RLIM_ENABLE]
set_max_delay -from [get_pins {i_pkt_gen_mon/i_gen_top/i_packet_generator/ctl_tx_diagword_lanestat_reg[*]/C}] -to [get_pins DUT/inst/i_ilkn_top_inst/*/CTL_TX_DIAGWORD_INTFSTAT] 6.000
set_max_delay -from [get_pins {i_pkt_gen_mon/i_gen_top/i_packet_generator/ctl_tx_diagword_lanestat_reg[*]/C}] -to [get_pins {DUT/inst/ctl_tx_diagword_lanestat_1d_reg[*]/D}] 6.000
set_max_delay -from [get_pins i_pkt_gen_mon/i_gen_top/i_packet_generator/ctl_tx_enable_reg/C] -to [get_pins DUT/inst/i_ilkn_top_inst/*/CTL_TX_ENABLE] 6.000
create_generated_clock -name TX_FC_CLK -source [get_pins i_tx_oobfc/i_CORE/i_ODDRE1_CLK/C] -edges {1 3 5} [get_ports tx_fc_clk]
set_output_delay -clock [get_clocks TX_FC_CLK] -max 0.750 [get_ports {tx_fc_data tx_fc_sync}]
set_output_delay -clock [get_clocks TX_FC_CLK] -min -0.750 [get_ports {tx_fc_data tx_fc_sync}]
set_output_delay -clock [get_clocks TX_FC_CLK] -clock_fall -max -add_delay 0.750 [get_ports {tx_fc_data tx_fc_sync}]
set_output_delay -clock [get_clocks TX_FC_CLK] -clock_fall -min -add_delay -0.750 [get_ports {tx_fc_data tx_fc_sync}]
set_false_path -to [get_pins -of [get_cells {{i_rx_oobfc/i_RXCLKRESET/pipe_reg[*]} {i_rx_oobfc/i_RXCLKRESET/pipe2_reg[*]}}] -filter REF_PIN_NAME==PRE]
set_max_delay -datapath_only -from [get_pins -of [get_cells {*i_rx_oobfc/i_CORE/i_ACK/eventout_reg[*]}] -filter REF_PIN_NAME==C] -to [get_pins -of [get_cells {*i_rx_oobfc/i_CORE/i_REQ/i_SYNCER/meta_reg[*]}] -filter REF_PIN_NAME==D] 10.000
set_max_delay -datapath_only -from [get_pins -of [get_cells {*i_rx_oobfc/i_CORE/i_REQ/eventout_reg[*]}] -filter REF_PIN_NAME==C] -to [get_pins -of [get_cells {*i_rx_oobfc/i_CORE/i_ACK/i_SYNCER/meta_reg[*]}] -filter REF_PIN_NAME==D] 10.000
set_false_path -to [get_pins -of [get_cells {*i_rx_oobfc/i_CORE/*/i_SYNCER/meta_reg[*]}] -filter REF_PIN_NAME==D]
set_max_delay -datapath_only -from [get_pins -of [get_cells *i_rx_oobfc/i_CORE/i_RAM_POSEDGE/i_RAM_0/RAMA] -filter REF_PIN_NAME==CLK] -to [get_pins -of [get_cells {*i_rx_oobfc/i_CORE/i_RAM_POSEDGE/ram_rdata_int_reg[*]}] -filter REF_PIN_NAME==D] 10.000
set_max_delay -datapath_only -from [get_pins -of [get_cells *i_rx_oobfc/i_CORE/i_RAM_POSEDGE/i_RAM_0/RAMA_D1] -filter REF_PIN_NAME==CLK] -to [get_pins -of [get_cells {*i_rx_oobfc/i_CORE/i_RAM_POSEDGE/ram_rdata_int_reg[*]}] -filter REF_PIN_NAME==D] 10.000
set_max_delay -datapath_only -from [get_pins -of [get_cells *i_rx_oobfc/i_CORE/i_RAM_NEGEDGE/i_RAM_0/RAMA] -filter REF_PIN_NAME==CLK] -to [get_pins -of [get_cells {*i_rx_oobfc/i_CORE/i_RAM_NEGEDGE/ram_rdata_int_reg[*]}] -filter REF_PIN_NAME==D] 10.000
set_max_delay -datapath_only -from [get_pins -of [get_cells *i_rx_oobfc/i_CORE/i_RAM_NEGEDGE/i_RAM_0/RAMA_D1] -filter REF_PIN_NAME==CLK] -to [get_pins -of [get_cells {*i_rx_oobfc/i_CORE/i_RAM_NEGEDGE/ram_rdata_int_reg[*]}] -filter REF_PIN_NAME==D] 10.000
set_max_delay -datapath_only -from [get_pins -of [get_cells {*i_rx_oobfc/i_CORE/i_ACK/eventout_reg[*]}] -filter REF_PIN_NAME==C] -to [get_pins -of [get_cells {*i_rx_oobfc/i_CORE/i_RAM_POSEDGE/ram_rdata_int_reg[*]}] -filter REF_PIN_NAME==D] 10.000
create_clock -period 3.333 -name F1_SYS_300_REF_CLK1_P -waveform {0.000 1.667} [get_ports F1_SYS_300_REF_CLK1_P]
create_clock -period 4.000 -name init_clk_p -waveform {0.000 2.000} [get_ports init_clk_p]
create_clock -period 2.482 -name gt_ref_clk0_p -waveform {0.000 1.241} [get_ports gt_ref_clk0_p]
create_clock -period 10.000 -name rx_fc_clk -waveform {0.000 5.000} [get_ports rx_fc_clk]

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