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Newbie
Newbie
3,385 Views
Registered: ‎08-22-2017

Timing fails in Synthesis but not in Implementation

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Hi all,

 

I am new to Xilinx Vivado (used Quartus before) and I am having a timing problem in my design.

 

The problem is if I synthesize my design I get an error in the timing summary. If I then run the implementation I do not get any errors in the timing summary. Which one is correct? I think it is no good idea to ignore this warning, isn't it? But why does the implementation give no timing error? Maybe I am just using Vivado the wrong way...

 

Thank you!

 

Regards

Mathias

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Moderator
Moderator
5,430 Views
Registered: ‎09-15-2016

Hi @mps_kit

 

You should always follow the timing report after implementation is done. If your design passes timing after implementation that means it is safe to generate bitstream to dump on board.

The timing report after synthesis is just to give a heads up to the user that whether they need to modify the design /constraints or not based on the negative slack margin .

If the margin of negative slack after synthesis has very narrow margin then you can run implementation. Place and route tool can easily fix this.

But if you have some high voilations after synthesis then that mean you need to modify the design or constraints to produce better results.

Do refer chapter 5 of the below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug949-vivado-design-methodology.pdf

 

Hope this clears.

 

Regards

Rohit

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Rohit
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Moderator
Moderator
5,431 Views
Registered: ‎09-15-2016

Hi @mps_kit

 

You should always follow the timing report after implementation is done. If your design passes timing after implementation that means it is safe to generate bitstream to dump on board.

The timing report after synthesis is just to give a heads up to the user that whether they need to modify the design /constraints or not based on the negative slack margin .

If the margin of negative slack after synthesis has very narrow margin then you can run implementation. Place and route tool can easily fix this.

But if you have some high voilations after synthesis then that mean you need to modify the design or constraints to produce better results.

Do refer chapter 5 of the below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug949-vivado-design-methodology.pdf

 

Hope this clears.

 

Regards

Rohit

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

 

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

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Newbie
Newbie
3,361 Views
Registered: ‎08-22-2017

Hi @thakurr,

 

thank you for the fast answer. The negative slack was only a few hundred ps, so I think this the reason why the implementation finally worked.

 

Regards

Mathias

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Scholar
Scholar
3,312 Views
Registered: ‎02-27-2008

Yes,

 

Place and route is easily able to 'fix' a few hundred ps.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Guide
Guide
3,299 Views
Registered: ‎01-23-2009

Did you look at the violations after synthesis carefully? Were they setup violations (WNS) or hold violations (WHS). Hold time violations are not fixed until the route stage, so if you have a couple of ps (or even a small number of 100ps) of hold violation after synthesis (before place and route), this is nothing to be concerned about.

 

Avrum

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