I got a setup timing issue in my CMAC design as shown below.
But I don't understand why. Maybe I need some basic education.
My understanding is, for example path 125, total delay is 2.595ns is less than requirement 3.103ns, this should be ok for setup.
Is here any one can educate me what cause setup violation and how to fix it?
Thank you very much in advance!
BTW, the FPGA is xcku5p-ffvb676-1-i.
and below is the details of summary and clk path in path125