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Explorer
Explorer
1,502 Views
Registered: ‎06-09-2018

Timing problem and TNS

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Hi guys

 

In my design i have almost 2.5us TNS, and when i seen negative slack in different paths i found that : RST of my design was generated with one clk i.e. clk1 and this RST signal is propagated in FPGA and is imported to all inputs reset of my flipflops in design that clk of these FFs are different and not equal with clk1, in this circumstances what should i do?

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1,391 Views
Registered: ‎01-22-2015

Re: Timing problem and TNS

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@hrmt

 

       can i use double flopping circuit for this problem?

When you say “double flopping circuit”, I assume that you mean a two-flip-flop synchronizer (S2FF).

 

If you use a S2FF to pass a master-reset signal from the clk1-domain to the clk2-domain then the reset in the clk2-domain will:

  • come ON synchronously with clk2
  • go OFF synchronously with clk2

 

If this behavior is what you want, then all is well. However, consider the following consequences of using the S2FF to pass a reset from the clk1-domain to the clk2-domain.

  1. If the passed-reset feeds asynchronous resets in the clk2 domain then these asynchronous resets will behave as synchronous resets.  
  2. If the master reset is ON for less than two cycles of clk2 then you may need a pulse stretcher on the master reset to ensure that it passed with enough width into the clk2 domain
  3. During power-up, unusually close edges for the not-yet-stable clk2 could cause the S2FF to fail and pass metastability into the clk2-domain instead of a clean reset-ON signal.
  4. If you are using another S2FF to pass the reset from the clk2-domain to a clk3-domain, then consider what happens if clk3 comes-up (eg. at power-up) before clk2. In this situation, circuits in the clk3 domain may operate for a while before being reset when clk2 comes-up.

 

If instead, you use a reset-bridge to pass the master-reset from the clk1-domain to the clk2-domain then the reset in the clk2-domain will:

  • come ON simultaneously with the master-reset
  • come ON asynchronously with clk2
  • go OFF synchronously with clk2

 

The reset-bridge is usually preferred over the S2FF for passing a reset signal between clock domains or for passing an asynchronous reset into a clock domain.

 

--This VHDL process creates the reset-bridge
RSB1: process(clk2, master_rst)
begin
    if(master_rst = '1') then
        meta_rst <= '1';
        out_rst <= '1';         --out_rst comes ON asynchronously with master_rst
    elsif rising_edge(clk2) then 
        meta_rst <= '0';         
        out_rst <= meta_rst;    --out_rst comes OFF synchronously with clk2
    end if;                        
end process RSB1;
--This VHDL process creates the 2-flip-flop synchronizer S2FF: process(clk2) begin if rising_edge(clk2) then meta_2ff <= master_rst; --meta_2ff may have metastability out_2ff <= meta_2ff; --but out_2ff will be stable end if; end process S2FF;

reset_bridge.jpg

 

sync_2ff.jpg

14 Replies
Moderator
Moderator
1,490 Views
Registered: ‎01-16-2013

Re: Timing problem and TNS

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Hi,

 

You need proper reset network/logic.

Refer UG949.

 

Thanks,
Yash

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1,473 Views
Registered: ‎01-22-2015

Re: Timing problem and TNS

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@hrmt

 

It is common to use a global reset (often called a Power-ON Reset (POR)) to reset many of the flip-flops in your design. As @yashp says, careful distribution of the POR is needed to make it work properly and to avoid problems with timing analysis.

 

Your particular question is about sending the POR from circuits that are clocked by clk1 to circuits that are clocked by clk2. This is called a clock-domain crossing (CDC) and you must often insert special circuits at these crossings to avoid problems. For the POR CDC, we usually use a circuit called the reset-bridge. You will find a nice description of the POR and of the reset-bridge in the EETimes article <here>. You can also create the reset-bridge using the XPM_CDC_ASYNC_RST primitive described in UG953.

 

A bigger question is, “How do you generate the POR?”. You will find discussions of this and other reset-related topics in the following recent posts.

 

https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Demystifying-Resets-Synchronous-Asynchronous-other-Design/ba-p/882252

 

https://forums.xilinx.com/t5/Implementation/Practical-considerations-regarding-reset-circuit-implementation/td-p/883389

 

Cheers,

Mark

Explorer
Explorer
1,445 Views
Registered: ‎06-09-2018

Re: Timing problem and TNS

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thank you so much markg@prosensing.com but one question : can i use double flopping circuit for this problem?

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1,436 Views
Registered: ‎01-22-2015

Re: Timing problem and TNS

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@hrmt

 

Please note that the reset-bridge circuit is not a "double flopping circuit" synchronizer.  However, the reset-bridge has a built-in synchronizer.

 

Since the reset-bridge also acts as a synchronizer, you can use more than two flip-flops in the reset-bridge to make it more reliable (improve its ability to prevent metastability from reaching the destination clock-domain). If you are using the XPM_CDC_ASYNC_RST primitive to create the reset-bridge then the number of flip-flops is controlled by the DEST_SYNC_FF attribute of this primitive.  However, two flip-flops usually makes a very reliable reset-bridge.  You’ll find a nice lecture and some calculations for Mean Time Between Failure (MTBF) of the two flip-flop synchronizer <here>

 

You must set the property, ASYNC_REG=TRUE, for each flip-flop used in the reset-bridge to make it work properly as a synchronizer. If you are using the XPM_CDC_ASYNC_RST primitive then this is done automatically for you.  However, if you have written the RTL for the reset-bridge yourself then you can use the following constraint, which is placed in your Vivado project’s XDC file.

set_property ASYNC_REG true [get_cells <your_flip_flop>]

 

Finally, the POR (ie. master reset) input to the reset-bridge is often asynchronous with any of the clocks in your Vivado project. The properly constructed reset-bridge helps prevent metastability problems caused by this asynchronous input. However, Vivado timing analysis may still report negative slack for the timing path coming into the reset-bridge.  You can simply ignore this negative slack or (better) you can tell timing analysis to ignore (ie. not analyze) this path using an XDC constraint similar to the following.

set_false_path -to [get_cells <first_flip_flop_in_reset_bridge>]

 

Mark

1,392 Views
Registered: ‎01-22-2015

Re: Timing problem and TNS

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@hrmt

 

       can i use double flopping circuit for this problem?

When you say “double flopping circuit”, I assume that you mean a two-flip-flop synchronizer (S2FF).

 

If you use a S2FF to pass a master-reset signal from the clk1-domain to the clk2-domain then the reset in the clk2-domain will:

  • come ON synchronously with clk2
  • go OFF synchronously with clk2

 

If this behavior is what you want, then all is well. However, consider the following consequences of using the S2FF to pass a reset from the clk1-domain to the clk2-domain.

  1. If the passed-reset feeds asynchronous resets in the clk2 domain then these asynchronous resets will behave as synchronous resets.  
  2. If the master reset is ON for less than two cycles of clk2 then you may need a pulse stretcher on the master reset to ensure that it passed with enough width into the clk2 domain
  3. During power-up, unusually close edges for the not-yet-stable clk2 could cause the S2FF to fail and pass metastability into the clk2-domain instead of a clean reset-ON signal.
  4. If you are using another S2FF to pass the reset from the clk2-domain to a clk3-domain, then consider what happens if clk3 comes-up (eg. at power-up) before clk2. In this situation, circuits in the clk3 domain may operate for a while before being reset when clk2 comes-up.

 

If instead, you use a reset-bridge to pass the master-reset from the clk1-domain to the clk2-domain then the reset in the clk2-domain will:

  • come ON simultaneously with the master-reset
  • come ON asynchronously with clk2
  • go OFF synchronously with clk2

 

The reset-bridge is usually preferred over the S2FF for passing a reset signal between clock domains or for passing an asynchronous reset into a clock domain.

 

--This VHDL process creates the reset-bridge
RSB1: process(clk2, master_rst)
begin
    if(master_rst = '1') then
        meta_rst <= '1';
        out_rst <= '1';         --out_rst comes ON asynchronously with master_rst
    elsif rising_edge(clk2) then 
        meta_rst <= '0';         
        out_rst <= meta_rst;    --out_rst comes OFF synchronously with clk2
    end if;                        
end process RSB1;
--This VHDL process creates the 2-flip-flop synchronizer S2FF: process(clk2) begin if rising_edge(clk2) then meta_2ff <= master_rst; --meta_2ff may have metastability out_2ff <= meta_2ff; --but out_2ff will be stable end if; end process S2FF;

reset_bridge.jpg

 

sync_2ff.jpg

Explorer
Explorer
1,261 Views
Registered: ‎06-09-2018

Re: Timing problem and TNS

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Hi markg@prosensing.com

 

when i use RST Bridge Circuit my design Becomes unstable.

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1,234 Views
Registered: ‎01-22-2015

Re: Timing problem and TNS

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@hrmt

 

Is reset ON only during power-up of the FPGA?

 

Please show me constraints you have written for the reset bridge.

 

Is your design stable if you use the S2FF synchronizer instead of the reset bridge?

 

Please show me constraints you have written for the S2FF.

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Explorer
Explorer
1,208 Views
Registered: ‎06-09-2018

Re: Timing problem and TNS

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markg@prosensing.com

 

Is reset ON only during power-up of the FPGA?

what is your mean?

 

Please show me constraints you have written for the reset bridge.

what constraints should i write? i don't write any constraint for RST Bridge.

 

Is your design stable if you use the S2FF synchronizer instead of the reset bridge?

no, before using RST Bridge or S2ff my design was stable but when i use these methods my design becomes unstable.

 

 

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Registered: ‎01-22-2015

Re: Timing problem and TNS

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@hrmt

 

     what constraints should i write?

If you use the VHDL process, RSB1, from my post above to create the reset bridge then you should place the following constraints in your XDC file:

set_property ASYNC_REG true [get_cells meta_rst_reg]
set_property ASYNC_REG true [get_cells out_rst_reg]
set_false_path -to [get_cells meta_rst_reg]

The first two constraints cause the registers, meta_rst_reg and out_rst_reg, to be placed close together (within the same FPGA slice). This is necessary for the reset bridge to operate as a synchronizer and fight metastability. If you do not use the first two constraints, then the passed reset signal could be metastable – and this can cause your design to be unstable. The third constraint is optional. It tells Vivado timing analysis not to analyze the timing path coming into the reset bridge because, 1) you already know this path is a clock-domain crossing that it may fail timing analysis, and 2) you have properly taken care of the clock-domain crossing by using the reset bridge circuit.

 

     what is your mean?

Is your reset a “power-ON reset” (ie. reset=1 during power-up of FPGA and then reset=0 while FPGA is running)?   -or, while FPGA is running, does your RTL code sometimes toggle the reset between 1 and 0?

Explorer
Explorer
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Registered: ‎06-09-2018

Re: Timing problem and TNS

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markg@prosensing.com

 

while FPGA is running, my RTL code sometimes toggle the reset between 1 and 0.

 

and i use your constraints but design is unstable still.

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Registered: ‎01-22-2015

Re: Timing problem and TNS

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@hrmt

 

Is your entire design passing timing analysis?

 

You are sending reset signal from clk1-domain to clk2-domain. What is frequency of clk1 and clk2?

 

   …but design is unstable still.

Please describe “unstable”.

 

Is “unstable” coming from clk2-domain or clk1-domain?

 

Can you isolate “unstable” to a single VHDL process/component and show me this process/component?

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Explorer
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Registered: ‎06-09-2018

Re: Timing problem and TNS

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markg@prosensing.com

clks frequency in my design are: 25M, 12.5M, 2M, 256K

 

unstability is in 12.5M and 256K clk domains.

 

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Registered: ‎01-22-2015

Re: Timing problem and TNS

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@hrmt

 

Here are some things to try:

 

1) Instead of using the reset-bridge, try using the 2-flip-flop synchronizer described by the VHDL process called S2FF in my post above. For this synchronizer, use the following constraints:

set_property ASYNC_REG true [get_cells meta_2ff_reg] 
set_property ASYNC_REG true [get_cells out_2ff_reg] 
set_max_delay -datapath_only -from [get_cells master_rst_reg] -to [get_cells meta_2ff_reg] ppp

 

In the last constraint, “ppp” is a number equal to the shorter period of the two clocks involved. For example, if you are sending a reset from the 25MHz clock-domain to the 2MHz clock-domain, then ppp=(1/25e6)=40 because 40ns is the shorter period of the two clocks.

 

2) Ensure that the input, master_rst, to S2FF is coming directly from a register and not from combinational logic. When the input to S2FF comes from combinational logic (eg. LUT) then S2FF may not work properly (and could cause instability).

 

3) When you set reset=1 in your HDL, ensure that you are holding it in this state long enough. For example, if you are passing reset=1 from the 25MHz clock-domain to the 256K clock-domain then the HDL in the 25MHz clock domain should hold reset=1 for at least two cycles of the 256KHz clock, which is at least 196 cycles(!) of the 25MHz clock.

 

You have not described the “unstable” condition with enough detail for us to help you. Usually, “unstable” is a word we use when the design is failing timing analysis (ie. when TNS does not equal 0). I assume that you now have TNS=0?   If none of the above suggestions help then perhaps you should look beyond the reset for other causes of your “unstable” condition. Perhaps simulation of your HDL will help you troubleshoot the problem.

 

Good luck!
Mark

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Registered: ‎01-22-2015

Re: Timing problem and TNS

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@hrmt

 

You might be interested in the Vivado Clock Domain Crossings (CDC) report that is described on about page 79 of UG906.   This report gives structural analysis of the circuits (eg. S2FF) you are using to pass the reset from one clock-domain to another. One of the many checks it does is to ensure that input to each synchronizer is not coming from combinational logic (see CDC-10 in Table 2-3 of UG906).

 

You can receive the CDC report by first clicking “Open Implemented Design” and then from Vivado menus select “Tools > Report > Timing > Report CDC…”.

 

Mark

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