cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
daranda314
Visitor
Visitor
330 Views
Registered: ‎11-04-2019

Timing problem with GTP example project

Hi,

I've edited the example project for the GTP transceiver and tried to implemented on a AC701 board using a loop back connection and an external oscilator. The problem is that the sent and received data don't match and as I've been told here  https://forums.xilinx.com/t5/Serial-Transceivers/AC701-GTP-Loop-test-problem/td-p/1164081 the problem could be with the timing errors that my project has.

daranda314_0-1603392362279.png

As you can see, I have negative setup slack between the clockout0_1 (from TXOUTCLK 120 MHz)  and clk_out1_clk_wiz_0 (from DRP clock MMCM).

Is this something serious? This could be the cause of the issue? How can I solve that?

I uploaded my project here:

https://drive.google.com/file/d/13zEO6qxNs0q5_2t540yoCUQ-EAE2KEW8/view?usp=sharing

 

0 Kudos
Reply
1 Reply
yashp
Moderator
Moderator
234 Views
Registered: ‎01-16-2013

Hi,
The important point here is once you edit the example design this will no longer the example design and needs to be managed as a custom design.
From the snapshot you have shared you have setup violation of -8ns approx this looks like constraints issue.
The two clocks are in discussion where you are seeing the violations looks like asynchronous (a guess from timing numbers) and this CDC needs to be managed for proper data transfer.
Please refer UG949 for CDC and UG903 for constraints.

Thanks,
Yash