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Visitor dd5a
Visitor
403 Views
Registered: ‎08-07-2018

Timing violation for axi_pcie_0 IP block

I am getting a timing violation that I don't understand because it seems to be inside the axi_pci IP block and that is largely out of my control (Or is it?).

Specifically, the violation is under Intra-Clock path -> clk_125mhz ->Setup.  There are 10 failed paths.

The Design is simple - a simple BRAM mapped to the PCIe bus on a single board computer.  The design as presented in the block diagram works with the violation - I am able to write/read to any address in the BRAM.  I've attached both the block diagram for the design and the timing violations.  Any help with this would be much appreciated.

Thanks

Block Diagram Capture 1.PNG
Implemented Design with timings Capture 1.PNG
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2 Replies
Highlighted
Explorer
Explorer
346 Views
Registered: ‎07-18-2018

Re: Timing violation for axi_pcie_0 IP block

Hi dd5a,

     Can you grab the details of the path that is failing? It's hard to know from what you provided what the failure would be.

I'd recommend doing the following command:

report_timing -from [get_pins <Right click on the name of the from in the report violation and paste it here>] -to [get_pins <do the same thing for the to side] -nworst 1 -max_paths 1

It will print it in text to the tcl console, copy and paste the path details it provides.

The second thing to do, would be to look at any of the IP constraints, and just double check that it doesn't appear that any of the false_paths, or max_delays or set_clock-groups would be trying to describe them. 

If it is, it might not be applying correctly, if it isn't, then seeing the path details itself would give some ideas as to what might be happening.

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Visitor dd5a
Visitor
330 Views
Registered: ‎08-07-2018

Re: Timing violation for axi_pcie_0 IP block

Hi evant_nq,  

Thanks for the reply.  Below is the report_timing output for one of the failing paths.  Also, maybe you can give a bit more details on what you think I should be looking for in the .xdc files.  My user .xdc file hasn't defined any clocks (yet), just pins.  Everything else was generated automatically by the compiler.

report_timing -from [get_pins PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/pcie_7x_i/pcie_block_i/USERCLK2] -to [get_pins {PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_pcie_mm_s/comp_slave_bridge/comp_slave_read_cpl_tlp/tag_active_reg[6,13][4]/CE}] -nworst 1 -max_paths 1
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-78] ReportTimingParams: -from_pins -to_pins -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014
| Date : Mon Dec 17 18:16:53 2018
| Host : DANNEWPRECISION running 64-bit major release (build 9200)
| Command : report_timing -from [get_pins PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/pcie_7x_i/pcie_block_i/USERCLK2] -to [get_pins {PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_pcie_mm_s/comp_slave_bridge/comp_slave_read_cpl_tlp/tag_active_reg[6,13][4]/CE}] -nworst 1 -max_paths 1
| Design : top_level
| Device : 7a200t-ffg1156
| Speed File : -2 PRODUCTION 1.14 2014-09-11
| Temperature Grade : C
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Report

Slack (VIOLATED) : -0.240ns (required time - arrival time)
Source: PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/pcie_7x_i/pcie_block_i/USERCLK2
(rising edge-triggered cell PCIE_2_1 clocked by clk_125mhz {rise@0.000ns fall@4.000ns period=8.000ns})
Destination: PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_pcie_mm_s/comp_slave_bridge/comp_slave_read_cpl_tlp/tag_active_reg[6,13][4]/CE
(rising edge-triggered cell FDRE clocked by clk_125mhz {rise@0.000ns fall@4.000ns period=8.000ns})
Path Group: clk_125mhz
Path Type: Setup (Max at Slow Process Corner)
Requirement: 8.000ns (clk_125mhz rise@8.000ns - clk_125mhz rise@0.000ns)
Data Path Delay: 7.632ns (logic 2.564ns (33.596%) route 5.068ns (66.404%))
Logic Levels: 11 (CARRY4=4 LUT2=1 LUT3=1 LUT4=1 LUT5=1 LUT6=3)
Clock Path Skew: -0.369ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.620ns = ( 13.620 - 8.000 )
Source Clock Delay (SCD): 6.239ns
Clock Pessimism Removal (CPR): 0.251ns
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.124ns
Phase Error (PE): 0.000ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_125mhz rise edge)
0.000 0.000 r
GTPE2_CHANNEL_X0Y7 GTPE2_CHANNEL 0.000 0.000 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i/TXOUTCLK
net (fo=1, routed) 1.274 1.274 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/clk_txoutclk
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.081 1.355 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/txoutclk_i.txoutclk_i/O
net (fo=1, routed) 1.520 2.874 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/refclk
MMCME2_ADV_X0Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.077 2.951 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT0
net (fo=2, routed) 1.559 4.510 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/clk_125mhz
BUFGCTRL_X0Y0 BUFGCTRL (Prop_bufgctrl_I0_O)
0.081 4.591 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/O
net (fo=9118, routed) 1.648 6.239 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/pcie_7x_i/I8
PCIE_X0Y0 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/pcie_7x_i/pcie_block_i/USERCLK2
------------------------------------------------------------------- -------------------
PCIE_X0Y0 PCIE_2_1 (Prop_pcie_2_1_USERCLK2_CFGDEVCONTROLMAXREADREQ[1])
1.085 7.324 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/pcie_7x_i/pcie_block_i/CFGDEVCONTROLMAXREADREQ[1]
net (fo=61, routed) 1.125 8.449 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/pcie_7x_i/cfg_dev_control_max_read_req[1]
SLICE_X42Y212 LUT5 (Prop_lut5_I4_O) 0.105 8.554 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/pcie_7x_i/link_down_latch_i_37/O
net (fo=1, routed) 0.000 8.554 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/pcie_7x_i/n_0_link_down_latch_i_37
SLICE_X42Y212 CARRY4 (Prop_carry4_S[1]_CO[3])
0.444 8.998 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/pcie_7x_i/link_down_latch_reg_i_23/CO[3]
net (fo=1, routed) 0.000 8.998 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/pcie_7x_i/n_0_link_down_latch_reg_i_23
SLICE_X42Y213 CARRY4 (Prop_carry4_CI_CO[3])
0.100 9.098 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/pcie_7x_i/link_down_latch_reg_i_14/CO[3]
net (fo=1, routed) 0.000 9.098 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/pcie_7x_i/n_0_link_down_latch_reg_i_14
SLICE_X42Y214 CARRY4 (Prop_carry4_CI_CO[3])
0.100 9.198 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/pcie_7x_i/link_down_latch_reg_i_5/CO[3]
net (fo=1, routed) 0.000 9.198 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/pcie_7x_i/n_0_link_down_latch_reg_i_5
SLICE_X42Y215 CARRY4 (Prop_carry4_CI_CO[3])
0.100 9.298 f PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/pcie_7x_i/link_down_latch_reg_i_3/CO[3]
net (fo=4, routed) 0.655 9.953 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_pcie_mm_s/comp_slave_bridge/comp_slave_read_req_tlp/I607[0]
SLICE_X44Y212 LUT6 (Prop_lut6_I0_O) 0.105 10.058 f PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_pcie_mm_s/comp_slave_bridge/comp_slave_read_req_tlp/s_axis_rr_tvalid_q_i_1/O
net (fo=7, routed) 0.406 10.463 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/axi_enhanced_top/tx_inst/tx_arbiter/sig_m_axis_rr_tvalid
SLICE_X45Y205 LUT2 (Prop_lut2_I1_O) 0.105 10.568 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/axi_enhanced_top/tx_inst/tx_arbiter/rdreq_cpl_correlateSM_cs[1]_i_3/O
net (fo=1, routed) 0.112 10.680 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/axi_enhanced_top/tx_inst/tx_arbiter/n_0_rdreq_cpl_correlateSM_cs[1]_i_3
SLICE_X45Y205 LUT6 (Prop_lut6_I1_O) 0.105 10.785 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.pcie_top_i/axi_enhanced_top/tx_inst/tx_arbiter/rdreq_cpl_correlateSM_cs[1]_i_2/O
net (fo=32, routed) 0.561 11.346 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_pcie_mm_s/comp_slave_bridge/comp_slave_read_cpl_tlp/sig_m_axis_rr_tready
SLICE_X46Y201 LUT3 (Prop_lut3_I2_O) 0.105 11.451 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_pcie_mm_s/comp_slave_bridge/comp_slave_read_cpl_tlp/rdreq_cpl_correlateSM_cs[0]_i_3/O
net (fo=33, routed) 1.039 12.490 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_pcie_mm_s/comp_slave_bridge/comp_slave_read_cpl_tlp/O9
SLICE_X72Y196 LUT6 (Prop_lut6_I3_O) 0.105 12.595 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_pcie_mm_s/comp_slave_bridge/comp_slave_read_cpl_tlp/tag_active[6,1][8]_i_5/O
net (fo=27, routed) 0.755 13.350 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_pcie_mm_s/comp_slave_bridge/comp_slave_read_cpl_tlp/O12
SLICE_X71Y186 LUT4 (Prop_lut4_I2_O) 0.105 13.455 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_pcie_mm_s/comp_slave_bridge/comp_slave_read_cpl_tlp/tag_active[6,13][8]_i_2/O
net (fo=9, routed) 0.416 13.871 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_pcie_mm_s/comp_slave_bridge/comp_slave_read_cpl_tlp/n_0_tag_active[6,13][8]_i_2
SLICE_X71Y186 FDRE r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_pcie_mm_s/comp_slave_bridge/comp_slave_read_cpl_tlp/tag_active_reg[6,13][4]/CE
------------------------------------------------------------------- -------------------

(clock clk_125mhz rise edge)
8.000 8.000 r
GTPE2_CHANNEL_X0Y7 GTPE2_CHANNEL 0.000 8.000 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i/TXOUTCLK
net (fo=1, routed) 1.216 9.216 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/clk_txoutclk
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.077 9.293 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/txoutclk_i.txoutclk_i/O
net (fo=1, routed) 1.417 10.710 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/refclk
MMCME2_ADV_X0Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.073 10.783 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i/CLKOUT0
net (fo=2, routed) 1.488 12.270 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/clk_125mhz
BUFGCTRL_X0Y0 BUFGCTRL (Prop_bufgctrl_I0_O)
0.077 12.347 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/O
net (fo=9118, routed) 1.272 13.620 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_pcie_mm_s/comp_slave_bridge/comp_slave_read_cpl_tlp/I1
SLICE_X71Y186 r PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_pcie_mm_s/comp_slave_bridge/comp_slave_read_cpl_tlp/tag_active_reg[6,13][4]/C
clock pessimism 0.251 13.870
clock uncertainty -0.071 13.799
SLICE_X71Y186 FDRE (Setup_fdre_C_CE) -0.168 13.631 PCIe_Interface_Inst/PCIe_Interface_i/axi_pcie_0/U0/comp_axi_pcie_mm_s/comp_slave_bridge/comp_slave_read_cpl_tlp/tag_active_reg[6,13][4]
-------------------------------------------------------------------
required time 13.631
arrival time -13.871
-------------------------------------------------------------------
slack -0.240

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