I don't seem to understand how Vivado defines output delays. The timing constraints wizard shows this diagram:
The setup delay makes sense, and a setup analysis is supposed to be performed with the -max TCL switch.
First of all, the hold time in this diagram appears to be going in the wrong direction, it should extend to the right of the rising clock edge, not to the left if data is going to be captured on that edge.
Secondly, the constraints wizard places extra restrictions on the delays, like I cannot use 0 or a negative value. Also, -min must be less than -max, but I don't see any reason why a hold time would necessarily be less than a setup time.
For example, I have the following signals from an ARM EBI interface:
MCKI is a shared clock, NCS is an active low chip select input, and NWAIT is a combinational output from the FPGA. NWAIT can be extended for multiple clock cycles, but in order to be read properly it must have a setup time of 0.6ns and be held for at least 3.2ns after the rising edge of the clock.
In this case my hold time is longer than my setup time, making -min larger than -max in the TCL commands, which is invalid in Vivado.