Xilinx has created comprehensive UltraFast Design Methodology Guides that cover key principles, specific do's and don'ts, best practices, and ways to avoid pitfalls. In some topics, Xilinx provide real life use cases to illustrate concepts. The methodologies presented is a reflection of user experiences and learning gained from system development inside and outside of Xilinx.
The Design Closure section outlines key timing constraints and how to validate the constraints for your design, and the impact of the timing and physical constraints on the overall WNS/WHS in the timing report. It also outlines the different reporting mechanisms to determine the root cause of the timing violations, and to close timing on the highly congested, high fanout, and control set nets of the design.
Download the new UltraFast High-Level Design Methodology Guide today!