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Observer 918212269
Observer
508 Views
Registered: ‎10-28-2017

Ultrascale+ Fabric & Register Fmax

There is some data missing in the Ultrascale+ datasheets that was included in the 7 series datasheets. 

 

   - Max delay through individual CLB resources

   - Max frequency for LE flip flops 

  

When performing timing analysis with some high frequency designs, I found something interesting.

 

   - The timing characteristics for the flip flops in a speedgrade -3 Zynq Ultrascale+ matches the timing specifications of the 7 series       Kintex perfectly. They both indicate the same exact Fmax of 1.8 GHz.

 

So from 28 nm to 16 nm there is zero performance improvement in fabric resources? 

Why are the numbers exactly the same? This seems like an odd coincidence.  

 

Why is the fabric in all of these FPGAs capable of working at nearly double the speed, if not over double the speed, of any of the clock buffers?  

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Explorer
Explorer
315 Views
Registered: ‎07-18-2018

Re: Ultrascale+ Fabric & Register Fmax

Hi 918212269,

Are you just looking at the setup and hold requirement of a FF at a single process corner? Usually a single element such as a FF might be able to toggle much faster then what can be reliably achieved in a design across PVT.

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