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Observer michal_pereg
Observer
235 Views
Registered: ‎05-21-2018

Ultrascale ISERDES INTERNAL_CLKDIV hold violation

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Hi,

I have a design for ADC interface with the following:

1. ADC serial data interface

2. Data clock - 350Mhz

3. Frame clock - 50Mhz

I'm using 1:8 ISERDES with div_clk = 87.5Mhz generated by BUFGCE_DIV

I'm using Vivado 2018.1

I get inter clock hold violation from INTERNAL_CLKDIV to my design clk_div (ISERDES input clock and FDRE clock)

Can you please let me know how can I overcome this violation?

Attached full path timing report and schematic screenshot.

 

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Moderator
Moderator
212 Views
Registered: ‎11-04-2010

Re: Ultrascale ISERDES INTERNAL_CLKDIV hold violation

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Hi, @michal_pereg ,

How about inserting a BUFGCE_DIV(1:1) between BUFGCE and ISERDESE3/CLK(CLK_B) ?

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3 Replies
Moderator
Moderator
213 Views
Registered: ‎11-04-2010

Re: Ultrascale ISERDES INTERNAL_CLKDIV hold violation

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Hi, @michal_pereg ,

How about inserting a BUFGCE_DIV(1:1) between BUFGCE and ISERDESE3/CLK(CLK_B) ?

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Observer michal_pereg
Observer
184 Views
Registered: ‎05-21-2018

Re: Ultrascale ISERDES INTERNAL_CLKDIV hold violation

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Thank you! It worked!
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170 Views
Registered: ‎01-22-2015

Re: Ultrascale ISERDES INTERNAL_CLKDIV hold violation

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@michal_pereg 

Be sure to follow guidance found on page-120 of UG949 (v2019.1) that says:

IMPORTANT: To ensure safe timing between parallel BUFGCE_DIV cells where the BUFGCE_DIVIDE property is set to a value greater than 1, both buffers must use the same enable signal (CE) and the same reset signal (RST). Otherwise, the divided clocks might become phase shifted from one another in hardware, which is not reported by the Vivado tools.

Mark

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