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Explorer
Explorer
1,686 Views
Registered: ‎10-05-2010

Unconstrained pins for maximum delay due to constant clock

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I have an Artix 7 design that includes an AXI Performance monitor. 

When external events are enabled, there is a clock input ext_clk_x for each monitor slot. However, I do not have external events enabled. The schematic (after implementation) shows that the ext_clk clock signals are tied low. This causes unconstrained_internal_endpoint warnings in the timing summary because there is a constant clock. I know that I can ignore this, but I'd prefer to have some constraint that removes the warnings.

 

I found the clock net in the netlist and tried a set_false_path

set_false_path -through [get_pins system/system_i/axiMonitor/inst/GEN_Advanced_Mode.adavnced_mode_inst/ext_clk_1]

but that didn't remove the warnings.

Any suggestions on how to remove these warnings?

 

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Joe Samson

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Explorer
Explorer
1,636 Views
Registered: ‎10-05-2010

Re: Unconstrained pins for maximum delay due to constant clock

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I didn't mean that I wanted to blanket remove the warning, I meant that I wanted to add timing constraints to cover these warnings.

 

I did discover the proper constraint syntax

set_false_path -to [get_cells system/system_i/axiMonitor/inst/GEN_Advanced_Mode.adavnced_mode_inst/GEN_SLOT1.mon_fifo_ext_event1_inst/CDC_ENABLE_MCLK_INST/syncstages_ff_reg[*]]

It looks like I'll need about 70 wild-carded constraints to cover these 400+ warnings.

 

You may notice that there's a typo in an instance name used in this IP: 'adavnced' instead of 'advanced'.

 

I'll leave this topic open for a few days to see if any passer-by can suggest a more efficient syntax.

 

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Joe

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4 Replies
Xilinx Employee
Xilinx Employee
1,660 Views
Registered: ‎09-24-2017

Re: Unconstrained pins for maximum delay due to constant clock

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Hi @josephsamson

Since these warnings can be safely ignored, you can use set_msg_config command to suppress them, for example :

set_msg_config -id {[Vivado_Tcl 4-935]} –suppress

You can replace "Vivado Tcl 4-935" with your warning number.

BR,

Martin

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Explorer
Explorer
1,637 Views
Registered: ‎10-05-2010

Re: Unconstrained pins for maximum delay due to constant clock

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I didn't mean that I wanted to blanket remove the warning, I meant that I wanted to add timing constraints to cover these warnings.

 

I did discover the proper constraint syntax

set_false_path -to [get_cells system/system_i/axiMonitor/inst/GEN_Advanced_Mode.adavnced_mode_inst/GEN_SLOT1.mon_fifo_ext_event1_inst/CDC_ENABLE_MCLK_INST/syncstages_ff_reg[*]]

It looks like I'll need about 70 wild-carded constraints to cover these 400+ warnings.

 

You may notice that there's a typo in an instance name used in this IP: 'adavnced' instead of 'advanced'.

 

I'll leave this topic open for a few days to see if any passer-by can suggest a more efficient syntax.

 

---

Joe

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Guide avrumw
Guide
1,626 Views
Registered: ‎01-23-2009

Re: Unconstrained pins for maximum delay due to constant clock

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I am not sure you can fix this with a constraint.

 

The tool is complaining that there is no "clock" object propagating to the clock pins of these flip-flops. This isn't a path timing failure, but a timing engine consistency check...

 

Since the pin is tied to a constant, it is not possible to (and would be very confusing even if it was possible) to place a clock on this pin. So since there is no clock on it, this warning will exist - nothing else matters; the check is simple "Is there a clock propagating to the clock pin of this clocked object - if not, issue a warning".

 

The best solution is to remove the unused core - if it is unclocked, then it is useless. You can consider something like using an "ifdef" to remove it.

 

Otherwise (as far as I know) there is no other way to remove these warnings other than to suppress them with the mechanism (including the wildcards you need) suggested by @martinwe. (I presume you realized that the set_msg_config can take a wildcarded string to filter out specific warnings, rather than all warnings).

 

Avrum

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Explorer
Explorer
1,617 Views
Registered: ‎10-05-2010

Re: Unconstrained pins for maximum delay due to constant clock

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I was not able to remove the messages using the set_msg_config. These warnings do not show up in the message tab; they are part of the  unconstrained_internal_endpoints under the check timing heading in the timing summary. It may be confusing to call them messages or warnings, since those words have special meaning. They are entries in the timing summary's unconstrained internal endpoint list.

 

Since they are unconstrained endpoints, I thought the best solution would be to write the constraints.

 

I am able to remove the unconstrained internal endpoints entries by using 69 set_false_path constraints with the -to qualifier. I was hoping that it would be possible to do the same thing with a single -from or -through, but I haven't figured that one out.

 

I agree that the best approach would be to fix the source code, but it's a Xilinx-supplied IP (AXI Performance Monitor) and  I don't want to take on the responsibility of maintaining my patch for the life of my product. 

 

Maybe the best solution is to reconfigure the IP to enable external events which then exposes the clock signal. Connect the clock to a convenient clock source, then tie all the event qualifiers to constants. Hopefully Vivado optimizes the event circuitry all away. 

 

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Joe Samson

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