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Observer ridgemao
Observer
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Registered: ‎06-29-2016

Unexpected large cell delay in ENARDEN port of RAMB36E1

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Hello:

 

In the 2nd attached picture, the timing path is the latter part of the path from a flipflop's Q to a latch's D, then to a RAM's enable pin. You can see the Time Borrowing in the 1st attached picture.

 

In the 2nd attached picture, in the timing report, there is 12.5ns delay for the Delay Type RAMB36E1, at the destination port ENARDEN.

It looks like a setup time cited from the library, but it is impossiblly large. 

How can I avoid this 12.5ns delay ?

 

Thank you.

 

reg_to_latch.jpg
latch_to_ram.jpg
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Observer ridgemao
Observer
149 Views
Registered: ‎06-29-2016

Re: Unexpected large cell delay in ENARDEN port of RAMB36E1

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This is a bug in vivado 2014, vivado 2018 solved this bug.
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Observer ridgemao
Observer
150 Views
Registered: ‎06-29-2016

Re: Unexpected large cell delay in ENARDEN port of RAMB36E1

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This is a bug in vivado 2014, vivado 2018 solved this bug.
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