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Visitor
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Registered: ‎03-05-2019

VC707 Gives different values for each run

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Hi All,

 

I have a design which is tested in simulation and meets all timing requirement. However when I run the design on the board, sometimes it gives expected results, but sometimes it gives wrong results for the same set of inputs.

Please let me know what could be the possible cause for this and a work around for the same.

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Moderator
Moderator
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Registered: ‎03-16-2017

Hi @fpgalab ,

I believe you are designing with Vivado. 

One point of debugging this issue: Do you have CDCs (Clock Domain Crossing) in your design? If yes then are they all safely synchronoized? You can check it by checking report_cdc report either in VIvado GUI or by TCL. 

Unsafe CDCs may cause metastability in outputs which will be seen on board. Hence, you may require proper synchronization and async_reg property on those paths which will be shown in that report.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.

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Moderator
Moderator
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Registered: ‎04-18-2011

Hi @fpgalab 

I've moved this to the timing analysis board. 

I think you will get good help here. 

Try to remember the tool is only as good as the constraints you give it. 

If your constraints do not match very well the real world then you are going to run into trouble. 

for example. the tool assume an input clock with low jitter. if this is not the case on the board then a path where it says it meets the contraints and the timing is met, albeit with not much margin, can quickly become a failing path if there is too much clock jitter. 

Another example is where the designer comes along and puts an exception on a path, like set_max_delay, what some people don't realise is that this breaks the default timing and imposes a new constraint on a path namely, if the delay is less than a max you give it then the path passes and there is no more about it. 

In real life this could be a genuine path that will violate in the real world. 

Please start by doing this:

check the timing report for unconstrained paths

check for paths that show up with no clock

report_clock_interaction - this will tell you about any paths where the launch and capture edges are not the same and if you have put any exceptions on them. 

Keith 

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Moderator
Moderator
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Registered: ‎03-16-2017

Hi @fpgalab ,

I believe you are designing with Vivado. 

One point of debugging this issue: Do you have CDCs (Clock Domain Crossing) in your design? If yes then are they all safely synchronoized? You can check it by checking report_cdc report either in VIvado GUI or by TCL. 

Unsafe CDCs may cause metastability in outputs which will be seen on board. Hence, you may require proper synchronization and async_reg property on those paths which will be shown in that report.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.

View solution in original post