UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
8,159 Views
Registered: ‎12-30-2008

Vivado pre-implementation timing analysis and closure techniques

Jump to solution

Hi,

 

Q01: Are there any pre-implementation timing analysis and closure techniques that I can apply, upon finding end-points with a negative slack in my design, as shown in the attached screenshot, for axi_dma_1?

 

201312260030-Vivado-2013.2-Pre-Implementation-Timing-Analysis.png

 

UG938 - Vivado Design Suite Tutorial - Design Analysis and Closure Techniques only talk about post-implementation timing analysis and closure, not for pre-implementation. The UltraFast design methodology also talks about fixing timing slack early on in the design.

 

Q02: Where can I find tutorial or resources on how to fix timing problems during static timing analysis?

 

Thanks in advance!

 

Regards,

 

Elvis Dowson

0 Kudos
1 Solution

Accepted Solutions
Highlighted
13,991 Views
Registered: ‎12-30-2008

Re: Vivado pre-implementation timing analysis and closure techniques

Jump to solution

Hi,

       I found the guidances in the UltraFast Design Methodology to be useful.

 

Xilinx UltraFast Design Methodology

 

 

UG938 - Vivado Design Suite Tutorial - Design Analysis and Closure Techniques v2013.4 was pretty useful for exploring the timing analysis and performing place and route features of Vivado, but it leaves one wanting for more, in terms of additional exercises.

 

Regards,

 

Elvis Dowson

0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
8,139 Views
Registered: ‎07-16-2008

Re: Vivado pre-implementation timing analysis and closure techniques

Jump to solution

The timing model from synthesis through implementation is common, it's just in synthesized design, the routing delay is estimated and the logic will possibly be optimized or changed in implementation.

 

So in post-synthesis result, we recommend that you focusing on validating the constraints, whether there're any unrealistic requirement (e.g. 200ps), whether there're missing CDC constraints, etc.

If the violation is caused by high levels of logic, consider optimizing HDL code prior to implementation.

 

Please review section "Baselining the Design" in UG949 (Ultrafast Design Methodology Guide).

 

For closure techniques, please have a look at UG906.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
13,992 Views
Registered: ‎12-30-2008

Re: Vivado pre-implementation timing analysis and closure techniques

Jump to solution

Hi,

       I found the guidances in the UltraFast Design Methodology to be useful.

 

Xilinx UltraFast Design Methodology

 

 

UG938 - Vivado Design Suite Tutorial - Design Analysis and Closure Techniques v2013.4 was pretty useful for exploring the timing analysis and performing place and route features of Vivado, but it leaves one wanting for more, in terms of additional exercises.

 

Regards,

 

Elvis Dowson

0 Kudos