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buddha1987
Voyager
Voyager
7,956 Views
Registered: ‎10-25-2012

What does "add clock" mean in Edit Timing Constraints?

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In Vivado,  Edit Timing Constraints, create clock option,  there is an option "add clock", you can tick it or not. What does it mean if I tick it? (see attachment)

 

It confused me since I firstly think this means I want to add the clock into my target file, however that can be done through clicking  

"Apply".

 

Thanks very much.

1.png
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graces
Moderator
Moderator
12,013 Views
Registered: ‎07-16-2008

The -add is typically used when you attempt to define a different clock period requirement on the same object.

So let's take a slightly different example.

 

create_clock -period 10.000 -name system_clk_1 -waveform {0.000 5.000} [get_nets o_clk_g]
create_clock -period 5.000 -name system_clk_2 -waveform {0.000 2.500} -add [get_nets o_clk_g]

 

Without -add, the second constraint will override the first one, so that the period requirement of o_clk_g is 5 ns.

With add, clock name "system_clk_1" and "system_clk_2" coexist, and both requirement will be analyzed.

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
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graces
Moderator
Moderator
7,950 Views
Registered: ‎07-16-2008

You can type "create_clock -help" in Tcl console to see what "-add" option means.

 

  -add - (Optional) Define multiple clocks on the same source for
  simultaneous analysis with different clock waveforms. Use -name to specify
  the new clock to add. If you do not specify this option, the create_clock
  command will automatically assign a name and will overwrite any existing
  clock of the same name.

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------
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buddha1987
Voyager
Voyager
7,948 Views
Registered: ‎10-25-2012

Thanks, I checked it and try it in edit timing constraint. But I don't understand the description very well (maybe my English is bad). Let us take an example to help me to understand:

create_clock -period 5.000 -name system_clk_1 -waveform {0.000 2.500} [get_nets o_clk_g]
create_clock -period 5.000 -name system_clk_2 -waveform {0.000 2.500} -add [get_nets o_clk_g]

 

Does this mean I create two clocks in XDC "system_clk_1" and "system_clk_2" with the same source "o_clk_g"? Whay will happen if withouth the "-add" ?

 

Thanks very much.

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graces
Moderator
Moderator
12,014 Views
Registered: ‎07-16-2008

The -add is typically used when you attempt to define a different clock period requirement on the same object.

So let's take a slightly different example.

 

create_clock -period 10.000 -name system_clk_1 -waveform {0.000 5.000} [get_nets o_clk_g]
create_clock -period 5.000 -name system_clk_2 -waveform {0.000 2.500} -add [get_nets o_clk_g]

 

Without -add, the second constraint will override the first one, so that the period requirement of o_clk_g is 5 ns.

With add, clock name "system_clk_1" and "system_clk_2" coexist, and both requirement will be analyzed.

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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buddha1987
Voyager
Voyager
7,944 Views
Registered: ‎10-25-2012
Now I got it, thanks very much.
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