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liwenrui
Observer
Observer
14,833 Views
Registered: ‎06-24-2011

What is the timing constraints for input?

The up stream device is tp403 with the following output timing.

From the data sheet:  tsu(2) = 1 ns,  th(2) = 0.5 ns 

Fclock = 166MHz  ( Period=6 ns ).

 

Untitled.png

 

 

 

 

I have the following in the UCF file:

 

NET "dvii_clk" TNM_NET = dvii_clk;
TIMESPEC TS_dvii_clk = PERIOD "dvii_clk" 6 ns HIGH 50%;  


INST "dvii_data<0>" TNM = group_dvii;
INST "dvii_data<1>" TNM = group_dvii;

INST "dvii_data<2>" TNM = group_dvii;


TIMEGRP "group_dvii" OFFSET = IN 1 ns VALID 1.5 ns BEFORE "dvii_clk" RISING;

 

With above constaints, The timing score is 109920 and I get some wrong data from the input(dvii_data).  

 

And also,  I tried with this:

 

TIMEGRP "group_dvii" OFFSET = IN 6 ns VALID 6 ns BEFORE "dvii_clk" RISING;

 

With above constaints, The timing score is 0. But I still get wrong data(same error) from the input:

 

final.png

Picture:  The noise within the red mark shows there is wrong data from the dvii_data.

 

So, what should be the correct constraint for this input of FPGA?  Thanks for any idea.

 

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gszakacs
Instructor
Instructor
14,830 Views
Registered: ‎08-14-2007

Your first constraint looks correct.  The fact that you're not meeting the constraint means you need to fix the design, not change the constraint.  A timing score of zero against the wrong constraint won't magically make the design run.

 

You've got a pretty tight timing window, and it may be that you can't meet this constraint without the help of dynamic phase shifting, or dynamic input delay.  Usually the first thing to try is fixed delays / phase shift, and see if you can find values that work.  Without knowing how your clock is managed (or even which device you're using) I can't comment further on how to fix this.

-- Gabor
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liwenrui
Observer
Observer
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Registered: ‎06-24-2011

Thanks Gab.

 

The below is how I manage the clock:

Tsu(2) = 1 ns (min value)       th(2) = 0.5 ns ( min value )

 

structure.png

 

There is an ibufg at the input of DCM and a bufg for output of DCM.  The device is xc7K325-2.

 

But I still get noise on the input ( final result  after the fifo ).  What else can I do for this or what is the full constraints or structure for this input device?  

 

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gszakacs
Instructor
Instructor
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Registered: ‎08-14-2007

What you need to do is to look at the "datasheet" section of the post place&route timing report.  That should show the actual setup and hold requirements for dvii_data with respect to dvii_clk.  Then you need to adjust the phase of the clock to make the timing work.  If you need help with this, post your timing report (.twr or .twx file).

 

Once you've fixed the input timing, then you can see if there are other issues in the design that might be causing the image defects you're seeing.  Failing timing doesn't prove that the defects are caused by input timing.

-- Gabor
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liwenrui
Observer
Observer
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Registered: ‎06-24-2011

Many thanks Gab.

 

I recompiled my project and I get a timing score 33967.  I didn't change anything on the input part.  Below is part of the timing report but all other is similar just different path of same signal.   The bus "dvii_blue" is a part of the "dvii_data".

 

What can I do with this case to clear the timing score to 0?  

 

================================================================================
Timing constraint: TIMEGRP "group_dvii" OFFSET = IN 1 ns VALID 1.5 ns BEFORE COMP "dvii_clk" "RISING";
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
27 paths analyzed, 27 endpoints analyzed, 27 failing endpoints
27 timing errors detected. (27 setup errors, 0 hold errors)
Minimum allowable offset is 2.392ns.
--------------------------------------------------------------------------------

Paths for end point GEN_INPUT.gen_hdmi_iddr[2].IDDR_inst (ILOGIC_X0Y70.D), 1 path
--------------------------------------------------------------------------------
Slack: -1.392ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: dvii_blue<2> (PAD)
Destination: GEN_INPUT.gen_hdmi_iddr[2].IDDR_inst (FF)
Destination Clock: fmc_dvidp_dvii_clk_bufg rising at 0.000ns
Requirement: 1.000ns
Data Path Delay: 1.321ns (Levels of Logic = 1)(Component delays alone exceeds constraint)
Clock Path Delay: -0.920ns (Levels of Logic = 3)
Clock Uncertainty: 0.151ns

Clock Uncertainty: 0.151ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.104ns
Phase Error (PE): 0.092ns

Maximum Data Path at Slow Process Corner: dvii_blue<2> to GEN_INPUT.gen_hdmi_iddr[2].IDDR_inst
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
AK29.I Tiopi 1.312 dvii_blue<2>
dvii_blue<2>
dvii_blue_2_IBUF
ILOGIC_X0Y70.D net (fanout=1) 0.000 dvii_blue_2_IBUF
ILOGIC_X0Y70.CLK Tidock 0.009 GEN_INPUT.dvii_iddr_bus<2>
GEN_INPUT.gen_hdmi_iddr[2].IDDR_inst
------------------------------------------------- ---------------------------
Total 1.321ns (1.321ns logic, 0.000ns route)
(100.0% logic, 0.0% route)

Minimum Clock Path at Slow Process Corner: dvii_clk to GEN_INPUT.gen_hdmi_iddr[2].IDDR_inst
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
---------------------------------------------------- -------------------
AB27.I Tiopi 1.147 dvii_clk
dvii_clk
GEN_INPUT.inst_dcm_dvii_clk/clkin1_buf
MMCME2_ADV_X0Y1.CLKIN1 net (fanout=1) 0.986 GEN_INPUT.inst_dcm_dvii_clk/clkin1
MMCME2_ADV_X0Y1.CLKOUT0 Tmmcmcko_CLKOUT -6.771 GEN_INPUT.inst_dcm_dvii_clk/mmcm_adv_inst
GEN_INPUT.inst_dcm_dvii_clk/mmcm_adv_inst
BUFGCTRL_X0Y7.I0 net (fanout=1) 2.017 GEN_INPUT.inst_dcm_dvii_clk/clkout0
BUFGCTRL_X0Y7.O Tbccko_O 0.083 GEN_INPUT.inst_dcm_dvii_clk/clkout1_buf
GEN_INPUT.inst_dcm_dvii_clk/clkout1_buf
ILOGIC_X0Y70.CLK net (fanout=584) 1.618 fmc_dvidp_dvii_clk_bufg
---------------------------------------------------- ---------------------------
Total -0.920ns (-5.541ns logic, 4.621ns route)

--------------------------------------------------------------------------------

Paths for end point GEN_INPUT.gen_hdmi_iddr[5].IDDR_inst (ILOGIC_X0Y59.D), 1 path
--------------------------------------------------------------------------------
Slack: -1.375ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: dvii_blue<5> (PAD)
Destination: GEN_INPUT.gen_hdmi_iddr[5].IDDR_inst (FF)
Destination Clock: fmc_dvidp_dvii_clk_bufg rising at 0.000ns
Requirement: 1.000ns
Data Path Delay: 1.311ns (Levels of Logic = 1)(Component delays alone exceeds constraint)
Clock Path Delay: -0.913ns (Levels of Logic = 3)
Clock Uncertainty: 0.151ns

Clock Uncertainty: 0.151ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.104ns
Phase Error (PE): 0.092ns

Maximum Data Path at Slow Process Corner: dvii_blue<5> to GEN_INPUT.gen_hdmi_iddr[5].IDDR_inst
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
AK28.I Tiopi 1.302 dvii_blue<5>
dvii_blue<5>
dvii_blue_5_IBUF
ILOGIC_X0Y59.D net (fanout=1) 0.000 dvii_blue_5_IBUF
ILOGIC_X0Y59.CLK Tidock 0.009 GEN_INPUT.dvii_iddr_bus<5>
GEN_INPUT.gen_hdmi_iddr[5].IDDR_inst
------------------------------------------------- ---------------------------
Total 1.311ns (1.311ns logic, 0.000ns route)
(100.0% logic, 0.0% route)

Minimum Clock Path at Slow Process Corner: dvii_clk to GEN_INPUT.gen_hdmi_iddr[5].IDDR_inst
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
---------------------------------------------------- -------------------
AB27.I Tiopi 1.147 dvii_clk
dvii_clk
GEN_INPUT.inst_dcm_dvii_clk/clkin1_buf
MMCME2_ADV_X0Y1.CLKIN1 net (fanout=1) 0.986 GEN_INPUT.inst_dcm_dvii_clk/clkin1
MMCME2_ADV_X0Y1.CLKOUT0 Tmmcmcko_CLKOUT -6.771 GEN_INPUT.inst_dcm_dvii_clk/mmcm_adv_inst
GEN_INPUT.inst_dcm_dvii_clk/mmcm_adv_inst
BUFGCTRL_X0Y7.I0 net (fanout=1) 2.017 GEN_INPUT.inst_dcm_dvii_clk/clkout0
BUFGCTRL_X0Y7.O Tbccko_O 0.083 GEN_INPUT.inst_dcm_dvii_clk/clkout1_buf
GEN_INPUT.inst_dcm_dvii_clk/clkout1_buf
ILOGIC_X0Y59.CLK net (fanout=584) 1.625 fmc_dvidp_dvii_clk_bufg
---------------------------------------------------- ---------------------------
Total -0.913ns (-5.541ns logic, 4.628ns route)

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gszakacs
Instructor
Instructor
14,797 Views
Registered: ‎08-14-2007

Can you post the "datasheet" section of the timing report that shows setup to clock dvii_clk?

 

From the bit you posted, it looks like you need to advance the clock by about 1.4 ns.  However it's important to see the hold timing, and whether this will erase any hold slack.  With a hold time slack of at least 1.5 ns, you would be able to use a 90 degree clock from the DCM to fix the input setup timing.  With less hold time slack, the same fix would break the input hold timing.  If that's the case you might need to use dynamic phase shifting to find the correct sampling point.

-- Gabor
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liwenrui
Observer
Observer
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Registered: ‎06-24-2011

Is this part the "datasheet"?

 

Derived Constraints for TS_dvii_clk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_dvii_clk | 6.000ns| 3.000ns| 4.977ns| 0| 0| 0| 37018|
| TS_GEN_INPUT_inst_dcm_dvii_clk| 6.000ns| 4.977ns| N/A| 0| 0| 37018| 0|
| _clkout0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

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liwenrui
Observer
Observer
14,793 Views
Registered: ‎06-24-2011

Is this part the "datasheet"?

 timing.png

 

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gszakacs
Instructor
Instructor
14,788 Views
Registered: ‎08-14-2007

Here's a "data sheet" bit from one of my timing reports:

 

 Data Sheet report:
 -----------------
 All values displayed in nanoseconds (ns)
 
 Setup/Hold to clock CL1_CK
 ------------+------------+------------+------------+------------+------------------+--------+
             |Max Setup to|  Process   |Max Hold to |  Process   |                  | Clock  |
 Source      | clk (edge) |   Corner   | clk (edge) |   Corner   |Internal Clock(s) | Phase  |
 ------------+------------+------------+------------+------------+------------------+--------+
 CL1_A<0>    |   -0.666(R)|      FAST  |    2.411(R)|      SLOW  |CL1/cl_clk        |   0.000|
 CL1_A<1>    |   -0.633(R)|      FAST  |    2.346(R)|      SLOW  |CL1/cl_clk        |   0.000|
 ------------+------------+------------+------------+------------+------------------+--------+
 
 Setup/Hold to clock CL2_CK
 ------------+------------+------------+------------+------------+------------------+--------+
             |Max Setup to|  Process   |Max Hold to |  Process   |                  | Clock  |
 Source      | clk (edge) |   Corner   | clk (edge) |   Corner   |Internal Clock(s) | Phase  |
 ------------+------------+------------+------------+------------+------------------+--------+
 CL2_A<0>    |   -0.582(R)|      FAST  |    2.295(R)|      SLOW  |CL2/cl_clk        |   0.000|
 CL2_A<1>    |   -0.613(R)|      FAST  |    2.358(R)|      SLOW  |CL2/cl_clk        |   0.000|
 ------------+------------+------------+------------+------------+------------------+--------+

If you don't see a similar part of your report (it's normally near the end), then check the settings for TRCE:

 

 

-- Gabor
Data Sheet.PNG
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liwenrui
Observer
Observer
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Registered: ‎06-24-2011

Now I got the Data sheet report:

 

Setup/Hold to clock dvii_clk

 -------------+------------+------------+------------+------------+-----------------------+--------+ 
              |Max Setup to|  Process   |Max Hold to |  Process   |                       | Clock  | 
 Source       | clk (edge) |   Corner   | clk (edge) |   Corner   |Internal Clock(s)      | Phase  | 
 -------------+------------+------------+------------+------------+-----------------------+--------+ 
 dvii_blue<0> |    2.338(R)|      SLOW  |   -0.521(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_blue<1> |    2.344(R)|      SLOW  |   -0.526(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_blue<2> |    2.392(R)|      SLOW  |   -0.574(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_blue<3> |    2.373(R)|      SLOW  |   -0.556(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_blue<4> |    2.357(R)|      SLOW  |   -0.539(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_blue<5> |    2.375(R)|      SLOW  |   -0.558(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_blue<6> |    2.370(R)|      SLOW  |   -0.552(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_blue<7> |    2.346(R)|      SLOW  |   -0.527(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_de      |    2.172(R)|      SLOW  |   -0.453(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_green<0>|    2.364(R)|      SLOW  |   -0.546(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_green<1>|    2.368(R)|      SLOW  |   -0.550(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_green<2>|    2.353(R)|      SLOW  |   -0.536(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_green<3>|    2.341(R)|      SLOW  |   -0.523(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_green<4>|    2.339(R)|      SLOW  |   -0.522(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_green<5>|    2.331(R)|      SLOW  |   -0.514(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_green<6>|    2.362(R)|      SLOW  |   -0.543(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_green<7>|    2.136(R)|      SLOW  |   -0.417(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_hsync   |    2.177(R)|      SLOW  |   -0.458(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_red<0>  |    2.132(R)|      SLOW  |   -0.413(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_red<1>  |    2.121(R)|      SLOW  |   -0.403(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_red<2>  |    2.129(R)|      SLOW  |   -0.410(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_red<3>  |    2.121(R)|      SLOW  |   -0.402(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_red<4>  |    2.142(R)|      SLOW  |   -0.424(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_red<5>  |    2.109(R)|      SLOW  |   -0.392(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_red<6>  |    2.165(R)|      SLOW  |   -0.446(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_red<7>  |    2.122(R)|      SLOW  |   -0.404(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 dvii_vsync   |    2.088(R)|      SLOW  |   -0.370(R)|      FAST  |fmc_dvidp_dvii_clk_bufg|   0.000| 
 -------------+------------+------------+------------+------------+-----------------------+--------+ 

TIMEGRP "group_dvii" OFFSET = IN 1 ns VALID 1.5 ns BEFORE COMP "dvii_clk" "RISING";

 Worst Case Data Window 2.022; Ideal Clock Offset To Actual Clock 1.131;  
 ------------------+------------+------------+------------+------------+---------+---------+-------------+ 
                   |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset| 
 Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  | 
 ------------------+------------+------------+------------+------------+---------+---------+-------------+ 
 dvii_blue<0>      |    2.338(R)|      SLOW  |   -0.521(R)|      FAST  |   -1.338|    1.021|       -1.180| 
 dvii_blue<1>      |    2.344(R)|      SLOW  |   -0.526(R)|      FAST  |   -1.344|    1.026|       -1.185| 
 dvii_blue<2>      |    2.392(R)|      SLOW  |   -0.574(R)|      FAST  |   -1.392|    1.074|       -1.233| 
 dvii_blue<3>      |    2.373(R)|      SLOW  |   -0.556(R)|      FAST  |   -1.373|    1.056|       -1.215| 
 dvii_blue<4>      |    2.357(R)|      SLOW  |   -0.539(R)|      FAST  |   -1.357|    1.039|       -1.198| 
 dvii_blue<5>      |    2.375(R)|      SLOW  |   -0.558(R)|      FAST  |   -1.375|    1.058|       -1.217| 
 dvii_blue<6>      |    2.370(R)|      SLOW  |   -0.552(R)|      FAST  |   -1.370|    1.052|       -1.211| 
 dvii_blue<7>      |    2.346(R)|      SLOW  |   -0.527(R)|      FAST  |   -1.346|    1.027|       -1.187| 
 dvii_de           |    2.172(R)|      SLOW  |   -0.453(R)|      FAST  |   -1.172|    0.953|       -1.063| 
 dvii_green<0>     |    2.364(R)|      SLOW  |   -0.546(R)|      FAST  |   -1.364|    1.046|       -1.205| 
 dvii_green<1>     |    2.368(R)|      SLOW  |   -0.550(R)|      FAST  |   -1.368|    1.050|       -1.209| 
 dvii_green<2>     |    2.353(R)|      SLOW  |   -0.536(R)|      FAST  |   -1.353|    1.036|       -1.195| 
 dvii_green<3>     |    2.341(R)|      SLOW  |   -0.523(R)|      FAST  |   -1.341|    1.023|       -1.182| 
 dvii_green<4>     |    2.339(R)|      SLOW  |   -0.522(R)|      FAST  |   -1.339|    1.022|       -1.180| 
 dvii_green<5>     |    2.331(R)|      SLOW  |   -0.514(R)|      FAST  |   -1.331|    1.014|       -1.172| 
 dvii_green<6>     |    2.362(R)|      SLOW  |   -0.543(R)|      FAST  |   -1.362|    1.043|       -1.203| 
 dvii_green<7>     |    2.136(R)|      SLOW  |   -0.417(R)|      FAST  |   -1.136|    0.917|       -1.027| 
 dvii_hsync        |    2.177(R)|      SLOW  |   -0.458(R)|      FAST  |   -1.177|    0.958|       -1.067| 
 dvii_red<0>       |    2.132(R)|      SLOW  |   -0.413(R)|      FAST  |   -1.132|    0.913|       -1.023| 
 dvii_red<1>       |    2.121(R)|      SLOW  |   -0.403(R)|      FAST  |   -1.121|    0.903|       -1.012| 
 dvii_red<2>       |    2.129(R)|      SLOW  |   -0.410(R)|      FAST  |   -1.129|    0.910|       -1.020| 
 dvii_red<3>       |    2.121(R)|      SLOW  |   -0.402(R)|      FAST  |   -1.121|    0.902|       -1.012| 
 dvii_red<4>       |    2.142(R)|      SLOW  |   -0.424(R)|      FAST  |   -1.142|    0.924|       -1.033| 
 dvii_red<5>       |    2.109(R)|      SLOW  |   -0.392(R)|      FAST  |   -1.109|    0.892|       -1.001| 
 dvii_red<6>       |    2.165(R)|      SLOW  |   -0.446(R)|      FAST  |   -1.165|    0.946|       -1.055| 
 dvii_red<7>       |    2.122(R)|      SLOW  |   -0.404(R)|      FAST  |   -1.122|    0.904|       -1.013| 
 dvii_vsync        |    2.088(R)|      SLOW  |   -0.370(R)|      FAST  |   -1.088|    0.870|       -0.979| 
 ------------------+------------+------------+------------+------------+---------+---------+-------------+ 
 Worst Case Summary|       2.392|         -  |      -0.370|         -  |   -1.392|    0.870|             | 
 ------------------+------------+------------+------------+------------+---------+---------+-------------+ 
 
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liwenrui
Observer
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Registered: ‎06-24-2011

Why do I get the display very messy everytime?

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