07-04-2018 04:14 AM
07-04-2018 04:26 AM
Can you show us that reset port through synthesized design? Snapshots will be helpful to understand. And also provide the constraint file which you have applied.
07-04-2018 06:51 AM
WHat language / tools you using ?
My bet is that the reset signal is used some where in the code as a clock, the tools are quite good at noticing that.
BTW: that could be a latch you have created with the reset,
Have you looked through the outputs on the terminal window
particularly the warnings, anything strange, like latches inferred , signals removed that you think should not be ?
07-04-2018 07:16 PM
Please check the reset signal connectivity in implemented design. What is the fanout of the reset? Can it be that a BUFG is inserted?
07-04-2018 08:26 PM
07-04-2018 08:30 PM
07-04-2018 09:25 PM
And also provide the snapshot of timing constraint wizard where you see this reset as a clock.
07-04-2018 10:41 PM
Hi @hemangd ,
Sorry I have attached the wrong schematic Please find the attachemnts below
In your schematic, select the net right after the BUFG, and then go to "Net Properties -> Connectivity or Cell Pins" to see if this net drives any CLK pins of sequential elements.
07-04-2018 11:36 PM
Does it drive any G pin of latches?
07-16-2018 08:54 AM
If the timing constraint wizard is identifying the net as a clock, then it is most likely driving a clock (or gate of a latch) pin somewhere in the design.
The tools can help you find it - open the synthesized design and type:
show_objects [filter [all_fanout -flat -endpoints_only [get_ports CPU_RESET]] "IS_CLOCK && IS_LEAF"]