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700 Views
Registered: ‎11-06-2017

Worst pulse width slack

Hi,

 

I am seeing TPWS(pulse width slack) in my design, i just want to understand why i am getting this violation.

I have a design which has SPI interface, which required 200MHZ input exteranal clock. If i connected 200Mhz clock which is from PLL then i am seeing this violation, if i use 100MHZ clock instead there is no violation. And the spi clock to SPI interface is 50MHZ and spi frequency ration i kept 4:1.

FPGA: ZYNQ Ultrascale + MPSOC xczu19eg -ffve1924-3-e

 

 

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11 Replies
Moderator
Moderator
686 Views
Registered: ‎11-04-2010

Re: Worst pulse width slack

Hi, ranjithanih@gmail.com ,

Please post the snapshot of the WPWS vioaltion, it looks to exceed the highest frequency limitation of some primitives (Ex: IOB).

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668 Views
Registered: ‎11-06-2017

Re: Worst pulse width slack

Hi Hongh,

Thanks for the response.

Below find the attached screeshot of WPWS violation.

 

Capture.PNG
Capture_1.PNG
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639 Views
Registered: ‎11-06-2017

Re: Worst pulse width slack

Hi,
I have generated 200MHZ clock with other PLL, still the issue is same. Can You please provide some inputs from your end.
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Moderator
Moderator
626 Views
Registered: ‎11-04-2010

Re: Worst pulse width slack

Hi, ranjithanih@gmail.com ,

The reason is just the one I guessed.

It's the limitation of the IOB in the bank.

The highest frequency of the IOB register in the bank is 125MHz, and your 200Mhz exceeds the limitation, no matter which PLL you are using.

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622 Views
Registered: ‎11-06-2017

Re: Worst pulse width slack

Hi hongh,

Here which IOB  we are talking about ?

I will try with 125MHZ and i will let you know.

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Guide avrumw
Guide
610 Views
Registered: ‎01-23-2009

Re: Worst pulse width slack

The violations are all flagging cells that are named "HDIO_*" - these are the "High Density I/O". These are low performance I/O as documented in the appropriate "SelectIO User Guide" (i.e. UG571 for UltraScale). These are documented as 250Mbps maximum data rate - the implication is that they should do 250MHz SDR or 125MHz DDR - however, the error message seems to be saying that the fastest clock rate is 125MHz - I don't know if/how it can tell if you are using SDR or DDR (I would have thought that SPI would be SDR...)

Avrum

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589 Views
Registered: ‎11-06-2017

Re: Worst pulse width slack

I have tried with 125MHZ, there is no violation.

 

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585 Views
Registered: ‎11-06-2017

Re: Worst pulse width slack

Hi avrumw,

Thanks for the response,

I have tried with 125mhz then there is no violation, if i tried with 200mhz there will be violation. As per the Selectio userguide HD banks support 250MHZ but when i used 200mhz, seeing the violation at the IOB. 

If SPI is SDR, it should support 200MHZ clock right as you said.

And i have checked quad spi userguide, i observed below table. 

SPI_Freq_limitation.PNG

I hope the above table is applicable to ZYNQ ultrascale+ MPSOC devices also. Here ext_spi_clk supports max 100MHZ for -3 speedgrade devices.

Any suggestions, i am not understanding which is cousing the issue ?

SPI_Freq_limitation.PNG
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448 Views
Registered: ‎11-06-2017

Re: Worst pulse width slack

Hi,

Issue got resolved by using below contraints.

set_property IOB FALSE [get_cells axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO0_I_REG]

The issue because of IOB packing. See thi forum post: https://forums.xilinx.com/t5/Timing-Analysis/kintex-ultrascale-quot-pack-reg-into-iob-quot-causing-pulse/td-p/862217

 

Moderator
Moderator
434 Views
Registered: ‎11-04-2010

Re: Worst pulse width slack

Hi, ranjithanih@gmail.com ,

Setting IOB property as "False" just means you intend to use the register in SLICE(FPGA fabric), instead of the register in IOB.

The regsiter in Slice can accept clock signal with much higher frequency.

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Guide avrumw
Guide
417 Views
Registered: ‎01-23-2009

Re: Worst pulse width slack

I suspect that unsetting the IOB property merely masks the problem - doesn't fix it.

I suspect (but can't conclusively prove) that the pulse width check is on the IOB flop only because they can only put a pulse width check on a clocked object (i.e. a flip-flop) - the tools simply have no internal mechanism of putting a pulse width check in the IOB (or the IBUF) itself.

However I the real limitation is on the IBUF and OBUF, not the IOB flip-flop. Take a look at UG571 Table 3-2 - all supported I/O standards (oddly except for HSUL_12, which I suspect is a typo) have footnote 1 which states that the I/O cannot operate above 250Mbps.

So by not using the IOB flip-flop, there is no pulse width check done by the tools. However, I suspect that your signal will not make it through the IBUF if it is faster than 250Mbps - regardless of whether it is clocked in the IOB or not.

Avrum

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