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Visitor toni_birka
Visitor
475 Views
Registered: ‎03-07-2019

ZYBO HDMI problem

Hello there,

I have a problem with saving the picture to the memory or reading the memory, I'm not pretty sure. I copied a block diagram from this link: https://www.hackster.io/adam-taylor/creating-a-zynq-or-fpga-based-image-processing-platform-e79394
Except that I'm not using the HDMI out, I'm sending the grayscale image over the UART, but I'm not getting the image as I wanted. There are some errors or outliers, I don't know how to name it, look at the picture below. What is the cause of it? 
There is also a critical warning about meeting the timing requirements and the timing summary is attached too.
The question is how can it be fixed?

Best regards,

Toni

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8 Replies
Scholar watari
Scholar
472 Views
Registered: ‎06-16-2013

Re: ZYBO HDMI problem

Hi @toni_birka 

 

Did you encounter screen tearing ?

If yes, I suggest you to use multifram function and other transfer method insted of UART.

 

BTW, it seems that your design has a lot of negative stacks. I suggest you to fix these problem, too.

 

Best regards,

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Visitor toni_birka
Visitor
457 Views
Registered: ‎03-07-2019

Re: ZYBO HDMI problem

Hi @watari,

can you check my function for sending frames to see if there is a chance of screen tearing? I'm stopping the VDMA while sending the data. I need to mention that it is not required to operate in real time, e.g. ZYBO sends an image every hour.

All my negative stacks are related to inputs and outputs, which you can see on the picture below. Can you suggest me how can I fix it? I've never done it before. :) 

Best regards,
Toni

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Scholar watari
Scholar
447 Views
Registered: ‎06-16-2013

Re: ZYBO HDMI problem

Hi @toni_birka 

 

Did you compile your design by SDx or VivadoHLS ?

If yes, it seems that your design lack gen_lock or multi frame setting.

 

Best regards,

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Visitor toni_birka
Visitor
442 Views
Registered: ‎03-07-2019

Re: ZYBO HDMI problem

Hi @watari,

no, I didn't.
I thought VivadoHLS is used for creating IPs.
How can I use it for compiling designs?

Best regards,
Toni
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Scholar watari
Scholar
434 Views
Registered: ‎06-16-2013

Re: ZYBO HDMI problem

Hi @toni_birka 

 

Can you share block diagram around VDMA ?

 

Best regards,

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Visitor toni_birka
Visitor
430 Views
Registered: ‎03-07-2019

Re: ZYBO HDMI problem

Hi @watari,

here you go...

Best regards,
Toni

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Scholar watari
Scholar
412 Views
Registered: ‎06-16-2013

Re: ZYBO HDMI problem

Hi @toni_birka 

 

The route cause is as below.

 

1. Very slow speed to transfer data via UART.

2. Don't use gen_lock function in VDMA and multiple buffer.

 

# About 1

I strongly recommend to use other way to transfer data to host instead of UART. ex. USB 2.0 or 3.0.

If using UART, I suggest you to turn off to wrtie streaming data via VDMA.

 

# About 2

Even if you transfer data via USB 2.0 or 3.0, transaction time is over one frame (16ms). You encounter same isssue.

I suggest you to use genlock function and multiple buffer in VDMA.

 

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842252/AXI+VDMA+Standalone+Driver

https://www.xilinx.com/products/intellectual-property/axi_video_dma.html

https://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v6_3/pg020_axi_vdma.pdf

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Video-Series-24-Using-the-AXI-VDMA-in-Triple-Buffer-Mode/ba-p/938327

 

Best regards,

 

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Visitor peterk
Visitor
398 Views
Registered: ‎04-08-2018

Re: ZYBO HDMI problem

There are unconstraint I/Os so the negative timing slack may not be problem with I/Os. I would definitely resolve them.

To isolate the source of the problem, you can load a static image (checker board) to the frame buffer memory and then sent it over the UART.

Peter Kwan, Senior FPGA Engineer
Designlinx Hardware Solution, Inc