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Visitor
Visitor
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Registered: ‎05-22-2014

Zynq-7020 BUFMR Min Period Violation

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I'm using a Zynq-7020 (xc7z020clg484-1), and I'm trying to use a BUFMR to forward a 500 MHz clock signal from an MMCM in one bank to a BUFIO in an adjacent bank.  After routing, I'm getting a timing violation on the BUFMR.  Specifically, it's a Pulse Width (Min Period) violation.  Vivado (2017.4) says the minimum required period is 2.155 ns, which translates to 464 MHz. 

CaptureTemp.JPG

According to the Data Sheet (DS187 2018-07-02), "The maximum input frequency to the BUFR and BUFMR is the BUFIO Fmax frequency."  For -1 speed grade, Fmax_bufio is 600 MHz;  however, Fmax_bufh is 464 MHz, and Fmax_bufg is 464 MHz.  

So my question is, which is the correct Fmax for a BUFMR?  The Datasheet that says the BUFMR Fmax should be same as BUFIO (600 MHz), or Vivado (2017.4) which says Fmax is same as a BUFG/BUFH (464 MHz)?

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Zynq-7020 BUFMR Min Period Violation

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The documentation is correct. There has been similar speed file issues for different architecture like Artix-7. A CR has been filed to request speed file update.

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Visitor
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Registered: ‎05-22-2014

Re: Zynq-7020 BUFMR Min Period Violation

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[edit: deleted after editing original post]

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Visitor
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Registered: ‎05-22-2014

Re: Zynq-7020 BUFMR Min Period Violation

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[edit: deleted after editing original post]

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Contributor
Contributor
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Registered: ‎04-19-2016

Re: Zynq-7020 BUFMR Min Period Violation

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I'm having exactly the same issue on a 7014 with vivado 2019.1. Anybody know the answer?

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Zynq-7020 BUFMR Min Period Violation

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Looks to be a speed file issue. The speed file value doesn't match the documentation.

I'll file a CR to dev team.

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Contributor
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Registered: ‎04-19-2016

回复: Zynq-7020 BUFMR Min Period Violation

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Thanks.

Is there a way to disable the pulse width check? set_false_path doesn't seem to work. Or a way to edit the 'speed file'?

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

回复: Zynq-7020 BUFMR Min Period Violation

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To disable the pulse width check on this pin also disables other timing check related it, which is not recommended.

You can just ignore this false check on this pin.

-vivian

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Visitor
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Registered: ‎05-22-2014

回复: Zynq-7020 BUFMR Min Period Violation

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Can you confirm that the documentation is indeed correct? Or could it be a documentation issue?

Before ignoring a timing violation like this, it would be important to have a definitive statement from Xilinx.  "Looks to be a speed file issue" probably wouldn't cut it as the basis for ignoring a timing violation if it ultimately resulted in a failure in our product.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Zynq-7020 BUFMR Min Period Violation

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The documentation is correct. There has been similar speed file issues for different architecture like Artix-7. A CR has been filed to request speed file update.

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