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tomray
Observer
Observer
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Registered: ‎03-27-2014

component switching limit error for ISE 14.2

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When I use ISE 14.2 to analyze the Virtex 7 DDR3 memory interfaces, I encounter the following errors. Could someone tell me what is the problem and how to solve this. Component Switching Limit Checks: TS_ddr_clk_gen_inst_clkout1 = PERIOD TIMEGRP "ddr_clk_gen_inst_clkout1" TS_sys_clk / 1.66666667 HIGH 50%; Slack: -0.736ns (max period limit - period) Period: 6.000ns Max period limit: 5.264ns (189.970MHz) (Tdlycper_REFCLK) Physical resource: u_ddr3_8g_666/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate0/REFCLK Logical resource: u_ddr3_8g_666/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate0/REFCLK Location pin: IDELAYCTRL_X0Y4.REFCLK Clock network: u_ddr3_8g_666/clk_ref Slack: -0.736ns (max period limit - period) Period: 6.000ns Max period limit: 5.264ns (189.970MHz) (Tdlycper_REFCLK) Physical resource: u_ddr3_8g_666/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate2/REFCLK Logical resource: u_ddr3_8g_666/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate2/REFCLK Location pin: IDELAYCTRL_X0Y6.REFCLK Clock network: u_ddr3_8g_666/clk_ref Slack: -0.736ns (max period limit - period) Period: 6.000ns Max period limit: 5.264ns (189.970MHz) (Tdlycper_REFCLK) Physical resource: u_ddr3_8g_666/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate4/REFCLK Logical resource: u_ddr3_8g_666/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate4/REFCLK Location pin: IDELAYCTRL_X1Y1.REFCLK Clock network: u_ddr3_8g_666/clk_ref
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driesd
Xilinx Employee
Xilinx Employee
19,170 Views
Registered: ‎11-28-2007

Hi Tomray,

 

using a search in Document Navigator, here is the definition of Component Switching Limits in the UG612 - Timing Closure Userguide:

screenshot_001.jpg

In your case, you are violating the REFCLK maximum frequency of the IDELAYCTRL which should be 200MHz.

 

 

Best regards

Dries

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tomray
Observer
Observer
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Registered: ‎03-27-2014

It's my first time to post message. The error info above is not clear, so i post it again.

 

Component Switching Limit Checks: TS_ddr_clk_gen_inst_clkout1 = PERIOD TIMEGRP "ddr_clk_gen_inst_clkout1" TS_sys_clk / 1.66666667 HIGH 50%; 

 

Slack: -0.736ns (max period limit - period)

 

Period: 

6.000ns

Max period limit: 

5.264ns (189.970MHz) (Tdlycper_REFCLK)

Physical resource: 

u_ddr3_8g_666/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate0/REFCLK

Logical resource: 

u_ddr3_8g_666/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate0/REFCLK

Location pin: 

IDELAYCTRL_X0Y4.REFCLK

Clock network: 

u_ddr3_8g_666/clk_ref

 

 

 

Slack: -0.736ns (max period limit - period)

 

Period: 

6.000ns

Max period limit: 

5.264ns (189.970MHz) (Tdlycper_REFCLK)

Physical resource: 

u_ddr3_8g_666/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate2/REFCLK

Logical resource: 

u_ddr3_8g_666/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate2/REFCLK

Location pin: 

IDELAYCTRL_X0Y6.REFCLK

Clock network: 

u_ddr3_8g_666/clk_ref

 

 

 

Slack: -0.736ns (max period limit - period)

 

Period: 

6.000ns

Max period limit: 

5.264ns (189.970MHz) (Tdlycper_REFCLK)

Physical resource: 

u_ddr3_8g_666/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate4/REFCLK

Logical resource: 

u_ddr3_8g_666/u_iodelay_ctrl/u_idelayctrl_MapLib_replicate4/REFCLK

Location pin: 

IDELAYCTRL_X1Y1.REFCLK

Clock network: 

u_ddr3_8g_666/clk_ref

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driesd
Xilinx Employee
Xilinx Employee
19,171 Views
Registered: ‎11-28-2007

Hi Tomray,

 

using a search in Document Navigator, here is the definition of Component Switching Limits in the UG612 - Timing Closure Userguide:

screenshot_001.jpg

In your case, you are violating the REFCLK maximum frequency of the IDELAYCTRL which should be 200MHz.

 

 

Best regards

Dries

--------------------------------------------------------------------------------------------------------------------
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Give Kudos to a post which you think is helpful and reply oriented by clicking the star next to the post.

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avrumw
Expert
Expert
12,358 Views
Registered: ‎01-23-2009

Actually, you are violating the minimum frequency for the IDELAYCTRL.

 

The IDELAYCTRL must be clocked by a reference clock that is either 200MHz +/- 10MHz, or (for a -2 or -3 device only) you can also use a 300MHz clock +/- 10MHz.

 

The device switching limit is saying your period of 6ns is too large for the maximum period of (1/(190MHz)), which comes out to 5.264ns.

 

Avrum

 

 

driesd
Xilinx Employee
Xilinx Employee
12,349 Views
Registered: ‎11-28-2007

Good point Avrum!

Of course the MAXIMUM frequency :)

 

 

Thanks

Dries

--------------------------------------------------------------------------------------------------------------------
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tomray
Observer
Observer
12,344 Views
Registered: ‎03-27-2014

I have changed the reference clock to be 200MHz, and the error has gone.

 

Thanks a lot.

 

Another question: For Virtex 7-485T FPGA (-2), the reference clock for IDELAYCTRL must be 200MHz +/- 10MHz ?

Where could I find datasheet for this infomation ?

 

Thanks again for this.

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driesd
Xilinx Employee
Xilinx Employee
12,336 Views
Registered: ‎11-28-2007

Hi Tomray,

 

Typically such timing specifications are listed in the datasheet.

For Virtex-7, this is DS183:

screenshot_001.jpg

 

 

Best regards

Dries

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