My situation differs in that I only have an input bus to constrain, and I plan to source my external clock via a separate output from the CLK WIZ such that I can adjust the phase to the external device, and allow me to (hopefully) meet timing on this interface. See the attached diagram.
The CLK WIZ is set to output the ext_clk at -50 deg, so that its rising edges are ~1.4 ns before the internal 100 MHz clock. Is this the correct approach, especially with regard to the multicycle hold constraint? I figure I will need to tweak the numbers a bit to meet timing, but I'm fearful I'm overlooking something.
This is for a lab setup only (not production) so I have some flexibility in adjusting the numbers after measuring delays and such on the HW.