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Observer
Observer
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Registered: ‎09-05-2018

constraints for synchronous external input bus; clock sourced by FPGA

I have a situation very similar to the one in this post:  https://forums.xilinx.com/t5/Timing-Analysis/Setup-violation-for-input-from-external-device/m-p/686401#M9536

My situation differs in that I only have an input bus to constrain, and I plan to source my external clock via a separate output from the CLK WIZ such that I can adjust the phase to the external device, and allow me to (hopefully) meet timing on this interface.  See the attached diagram.

My timing contraints are as follows:

create_generated_clock -name ext_clk -combinational -source [get_pins clk_wiz_i/CLKOUT2] [get_ports {ext_clk}]

[edit:  after more research I found that the '-combinational' option should not be used; replaced it with '-divide_by 1'.

create_generated_clock -name ext_clk -divide_by 1 -source [get_pins clk_wiz_i/CLKOUT2] [get_ports {ext_clk}]

set_input_delay -clock ext_clk -max 7 [get_ports {input_data[*]}]
set_input_delay -clock ext_clk -min 3 [get_ports {input_data[*]}]
set_multicycle_path 2 -setup -from [get_ports {input_data[*]}] -to [get_pins input_data_reg[*]/D]
set_multicycle_path 1 -hold -from [get_ports {input_data*]}] -to [get_pins input_data_reg[*]/D]

The CLK WIZ is set to output the ext_clk at -50 deg, so that its rising edges are ~1.4 ns before the internal 100 MHz clock.  Is this the correct approach, especially with regard to the multicycle hold constraint?  I figure I will need to tweak the numbers a bit to meet timing, but I'm fearful I'm overlooking something. 

This is for a lab setup only (not production) so I have some flexibility in adjusting the numbers after measuring delays and such on the HW.

 

 

adcTiming.jpg
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