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jonmccallum
Participant
Participant
9,650 Views
Registered: ‎12-10-2013

create_generated_clock error: Defaults source to non existent port in design

Hello All,

 

I am currently trying to run implementation in vivado.

 

I am taking in a synthesized netlist and converted xdc constraints file from synplify_pro.

 

When I am trying to load the synplify_pro converted xdc constraints file It is running into an error after trying to execute this line.

 

# 1026 : define_clock [get_nets {lsim.lsim_debug.fclk_div2}] -name {lsim_debug|fclk_div2_derived_clock} -ref_rise {0.000000} -ref_fall {40.000000} -uncertainty {0.000000} -period {80.000000} -clockgroup {default_clkgroup} -rise {0.000000} -fall {40.000000}

 

create_generated_clock -source [get_ports {OUT[0]}] -name {lsim_debug|fclk_div2_derived_clock} -divide_by 1 [ get_pins -filter {NAME =~ */C} -of_objects [get_cells -hier -filter {SYNOPSYS_XDC_1026 == TRUE}]]

 

The error is:

No clocks found for command 'get_clocks' -of_objects [get_ports {OUT[0]}]

 

 

This is coming from the project xdc file for the design. 

 

When I try to list_property [get_ports OUT[0]] It does not find the instance in the design.

 

Is this an error in the translation from the constraints in synplify to the constraints in vivado?

 

I am using vivado 2013.3.

 

Any insight to this would be helpfull.

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2 Replies
avrumw
Guide
Guide
9,640 Views
Registered: ‎01-23-2009

You have identified at least part of the problem - there is something wrong with the identifier in the get_ports command.

 

So the question is - what are the ports of your design really named?

 

The ports of your design are the primary inputs and outputs of your design. Do you expect one to be named OUT[0]? You should be able to see the list of ports of your design in the GUI by opening the netlist design, and using the menu Window -> I/O Ports. Alternatively you can use the Tcl command "get_ports" (with no options - that will return a list of the ports).

 

Aside from that, its hard to figure out what this thing is trying to do... It is creating a derived clock on the C pin of some cell that was tagged in the netlist by Synplify, but the source of the clock is some port named OUT[0]. Its hard to imagine a derived clock based on an output clock being used for an internal cell, and its a bit odd that you would have an input port named OUT[0]... So what is it that should be done here? What is this generated clock for? Why does the clock name have "div2" in it, but yet the generated clock is not divided? What is lsim_debug - does the fact that it has the word debug in it mean anything?

 

This is really all about your design. Without knowing what the design is, its going to be impossible for anyone (other than you) to debug what this constraint is really supposed to do. Once we know that, we can say if it is a Synplify bug, a Vivado bug, or something wrong with your design.

 

Avrum

 

 

 

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liubo_fpga
Explorer
Explorer
9,599 Views
Registered: ‎04-28-2013

You can check if port OUT[0] does existed in your desin. It seems that get_ports OUT[0]  get nonsense.

 

nonsense
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