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6,321 Views
Registered: ‎03-27-2014

fanout limit is hardly met

Hi,

 

I have a high fanout signal in one of my IPs (a clock enable signal being routed to several DSP slices, the default fanout was around 5k).

 

I moved to a non-default but still straightforward implementation strategy (Optimized_Retiming) which sets the fanout limit to 400, it dropped the fanout of that signal to 3k.

 

I kept that strategy and added a new constraint:

set_property MAX_FANOUT 100 [get_nets inst/tvalid_s]

now it dropped to 1k,

 

why is the tool not replicating that signal a lot more and meet the fanout-limit requirement of 400?

Should I drastically reduce the MAX_FANOUT property to achieve a better performance?

 

is phys_opt_design -force_replication_on_net [get_nets inst/tvalid_s] the only option?

G.W.,
NIST - Time Frequency metrology
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3 Replies
Scholar austin
Scholar
6,253 Views
Registered: ‎02-27-2008

Re: fanout limit is hardly met

g.w.

 

Fanout is not as important in a FPGA device as it would be in an ASIC.  In fact, it hardly matters at all as all paths are buffered.  Based on timing constraints the tools automatically optimize the path (replicate).  Since you do not seem to see that, it may be timing cannot be met, so it doesn't even try (gives up).  Or, your constraint is met, and it does not do any more work.

 

You may place the net on a BUFG to get the best timing (some newer families allow use of BUFG for any signal requiring low delay, low skew).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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5,991 Views
Registered: ‎03-27-2014

Re: fanout limit is hardly met

Hi @austin,

thanks for your time

 


@austin wrote:
Or, your constraint is met, and it does not do any more work.

in my case that is what happened

 


austin wrote:

Fanout is not as important in a FPGA device as it would be in an ASIC.  In fact, it hardly matters at all as all paths are buffered.


thank you I didn't know that, I was going through all things I could improve in my design, now I just forget about fanout since the tool seems to do quite a good job replicating some signals.

 


@austin wrote:

You may place the net on a BUFG to get the best timing (some newer families allow use of BUFG for any signal requiring low delay, low skew).


how would you decide which signal should be routed through a BUFG?

G.W.,
NIST - Time Frequency metrology
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Scholar austin
Scholar
5,986 Views
Registered: ‎02-27-2008

Re: fanout limit is hardly met

gw,

 

A reset, or a global enable is a good candidate to use a global or regional buffer.  If it is not used by everything, then using a BUFG is of little value,

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose