Hi i came acosse some puzzled issues on gated_clock_conversion operations：
I had to keep some logical implemented (write in verilog) clock gate module in design.
but the gate clock has multi-levers. that means the lowest gate clock input is derived from an another gate clcok.
i am not sue if i turn on the gated_clcok_conversion in sythesis setting, vivado tools could work well with such multi-lever gated clock hierachy.
Or is there are document to descipt such behavior or limitation. such as limited only 1 or 2 lever gate clock conversion.
What‘s the solution for this issue?
I have met the same problem.