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zxm02370303
Participant
Participant
7,522 Views
Registered: ‎03-26-2013

gated_clock_conversion work or not

Hi i came acosse some puzzled issues on gated_clock_conversion operations:

     I had to keep some logical implemented (write in verilog) clock gate module in design.

     but the gate clock has multi-levers. that means the lowest gate clock input is derived from an another gate clcok.

     i am not sue if i turn on the gated_clcok_conversion in sythesis setting, vivado tools could work well with such multi-lever gated clock hierachy.

     Or is there are document to descipt such behavior or limitation. such as limited only 1 or 2 lever gate clock conversion.

      Thank you.

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zhang_shuai@
Visitor
Visitor
460 Views
Registered: ‎02-22-2019

Hi 

What‘s the solution for this issue?

I have met the same problem.

 

Thanks,

Zhang

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