10-12-2018 12:24 AM
I have a question about Generated Clocks.
I have a design consisting of Clock Wizard IP(MMCM) with input clock 100MHz at "clk_in1". Now I generate 50MHz clock at output "clk_out1".
As per UG903(Page 88 and 89), Xilinx automatically derives constraints "create_generated_clock" for the clocks generated using PLL, MMCM etc.
But when I checked my design I cannot see any "create_generated_clock" constraints defined automatically for the "clk_out1".
Do I need to define them manually? If so, what does the UG903 actually mean?
10-12-2018 12:37 AM - edited 10-12-2018 12:48 AM
You only need to create_clock for the input port of MMCM, then the output clock of MMCM will be automatically generated. You don't need to create_generated_clock on the output of MMCM manually.
You can check the result of report_clocks to see the auto-generated clocks.
Ex: clk_pin_p is the input clock for MMCM, clk_rx_clk_core/clk_tx_clk_core is the output of MMCM.
10-12-2018 01:12 AM
Thank You for the answer. But I still have some questions though...
If the constraints are created automatically then why am I not seeing them in the list of all constraints. I still see total number of generated clock constraints as 0. (see image below-red box)
Also, I can see that the input clock constraint(input of MMCM) generated automatically(green box, design_1_clk_wiz_0_0.xdc file). I believe this is because in the IP editor window I have set information as 100MHz input clock. So, in this situation I don't have to even define the main input clock to MMCM input right?
10-12-2018 09:05 AM
You do not need these constraints in your file but for usage you might only want the clock on the port to be in your XDC file. As @hongh suggested, the tool will auto create generated clocks for MMCM output when the input clock has been defined in XDC. The quick way to check is using the MMCM example design provided in tool (like you are seeing the IP clk_wiz_0.xdc an input clock defined). So create_clock on the input port creates the clock on that port as well as automatically creates the generated clocks on the MMCM output and these clocks will exist.
But to get this clocks, there are some ways by which you can do. For eg. from the example design:
get_clocks -of_objects [get_pins clknetwork/inst/mmcm_adv_inst/CLKOUT0] --> MMCM output pin.
get_clocks clk_out1_clk_wiz_0 --> <generated_clock_name>
get_clocks -of_objects [get_nets clknetwork/inst/clk_out1_clk_wiz_0] --> Net connected to output of clocking wizard. (you can use top level net)
Also you can rename this auto propagated clock if needed for your design (AR-link).
Don't forget to reply, kudo, and mark the appropriate post as 'accept as solution'.
10-12-2018 09:13 AM
Hi, @mayflowers4972 ,
What you saw in "create_generated_clock" in "Edit timing constraints" only includes the manually create_generated_clock in the XDC(you create or IP carry), not includes the automatically generated clocks. So the number is 0.
You can just run "report_clocks" command in TCL CONSOLE to report all the clocks in the design.（The clocks you created or automatically generated）
10-12-2018 09:46 AM - edited 12-24-2019 07:41 AM
Vivado Tcl command like these are mechanisms of affecting the Vivado Design Database. When you execute a Tcl constraint command, the command itself is merely a mechanism for applying the constraint to the database. So when I do a "create_clock" command, the clock object is created in the database - the "create_clock" command itself is not the clock, it is the mechanism of creating the clock.
In "pure" SDC (like in Synopsys) from which XDC is derived, once the constraint is applied, the command itself is "gone" - it serves no more purpose - the constraint has affected the design detabase and is no longer needed.
However, in order to enable the GUI and project mode, Vivado keeps track of the Tcl commands - it keeps a Tcl constraint command database. It does this primarily for the ability to have the graphical helpers help you modify constraints. While they are used several times in the flow, what I said earlier is still true - these "tracked" Tcl commands are not the things that actually matter to the processes, it is their effects that matter.
Since this is managed so well by Xilinx, it is actually very difficult to perceive the difference between "the tracked Tcl commands" and "the effect they have on the design database" - so it is easy to assume they are the same thing. They are not. What you are seeing here is one place where this difference is visible. The "create_clock" Tcl command applied upstream of an MMCM has two effects:
So this one Tcl command generates several clocks. You can see this in the report_clocks command; the output clocks are "G" (generated) and "A" (automatically - i.e. not by a separate command). These are the effects on the design database.
But, there is still only one tracked Tcl command - the "create_clock" upstream of the MMCM.
10-18-2018 04:42 AM
Thank You for your answer.
Sorry for delayed response!.
So you mean to say that, these constraints for the generated clocks from MMCM IP need not appear in the constraints file but I can still use them in design for other purposes. Eg: If I want to apply a maxdelay constraint in case of CDC. Then I can use one of the mentioned methods to get the clocks and then formulate a max delay constraint in case there is CDC in the design.
Am I right?
10-18-2018 04:51 AM
Thank you for the explanation. I understand that it is important to know the effects of a particular command/constraint on the design. Like the example you gave for create_clock command and it's effect.
I did not actually understand what is "tracked Tcl commands". Does it mean the list of all constraints in the design? Does the "create_clock" command defined at the input of MMCM is an example of "tracked Tcl command"? and it's effects are
1) creating a clock object on the point attached and
2) creating (automatically) a number of derived clocks on the output of the MMCM
10-19-2018 04:48 AM - edited 12-24-2019 07:43 AM
I did not actually understand what is "tracked Tcl commands".
Exactly that - Vivado literally memorizes all constraint related Tcl commands that have been executed in the design. You can see all the "tracked Tcl commands" in the constraint window - with an opened synthesized or implemented design use Windows -> Timing Constraints. The "All constraints" portion (in the bottom half of the new window) shows all the tracked constraints. If you modify constraints using any means, it will add to/modify these tracked constraints, and, when you close the design, it will ask you if you want it to write these tracked constraints back to the appropriate XDC files.
This is how constraint management in Vivado (project mode) works. Constraints are brought into the database of tracked Tcl commands by
Whenever new constraints (ones that were not read from an XDC file that is part of the project) are added or existing constraints are modified in the database, the tool will ask you if you want to write them back to an XDC file when you close the design.
This mechanism is really separate from what the constraints actually do - which is constrain the design by adding information and/or objects to the design database (which is separate from the constraint database).
10-19-2018 06:34 AM
Thank you for the detailed explanation of how constraints are managed in vivado.
I did observe the list of all constraints(tracked ones) in the project(even the constraints supplied with IPs) at the lower half bottom of 'Timing Constraints' window. Any modification will prompt for the Update of corresponding XDC file in the upper half of the window. I believe the tracking feature of constraints in project mode is really a nice feature so that even after the constraint and it's effect are applied in the project and no longer needed we can still come back at some point of time and modify it as required. I never used non project mode and not sure what is the alternative to recall the tracked constraints!.