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schrepta
Observer
Observer
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Registered: ‎11-20-2013

how to constrain PLL outputs when frequency is a multiple of input and has phase delay

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Hi, I'm using vivado 2013.3, I have a PLL with clkin = 100MHz, clkout0 = 40 MHz, clkout1 = 20 MHz phase delayed 270 degrees.  I have a create clock for the 100 MHz input (at the fpga port pin).  I need to use create_generated_clock for the two outputs. 

 

For the clkout0, I have:

create_generated_clock -name clock40MHz -source [get_pins U0_adc_pll/plle2_adv_inst/CLKIN1] -multiply_by 8 -divide_by 20 [get_pins U0_adc_pll/plle2_adv_inst/CLKOUT0]. This is ok.

 

How do I constrain the clkout1?  create_generated_clock does not allow the -multiply_by and -edges parameters to be used together. How do I specify the different freq and phase shift? Or is there another approach or constraint type?

 

I've looked at the ug903-vivado-using-constraints documentation, and the user forums, did not find a solution.

Thanks

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muzaffer
Teacher
Teacher
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Registered: ‎03-31-2012
Actually you don't have to do anything. The timer knows how the PLL is configured and propagates the clocks properly. You only need to constrain the input clock.

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schrepta
Observer
Observer
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Registered: ‎11-20-2013

How about, using the clkout0 output as the reference, and using -edges and -edge_shift as follows? 

 

create_generated_clock -name clock20MHzp270 -source [get_pins U0_adc_pll/plle2_adv_inst/CLKOUT0]  -edges {1 3 5} -edge_shift {37.5 37.5 37.5} [get_pins U0_adc_pll/plle2_adv_inst/CLKOUT1]

 

comments?

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muzaffer
Teacher
Teacher
18,073 Views
Registered: ‎03-31-2012
Actually you don't have to do anything. The timer knows how the PLL is configured and propagates the clocks properly. You only need to constrain the input clock.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

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muzaffer
Teacher
Teacher
10,981 Views
Registered: ‎03-31-2012
not that you need it but for 20 MHz from 100 MHz your edges should be {1 6 11}; each step is 5ns so the total period is 5*(11-1) = 50 ns.
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schrepta
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Registered: ‎11-20-2013

Thank you.

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