cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
18,127 Views
Registered: ‎04-17-2017

how to write output delay constraints with device setup hold specified

Jump to solution

Hello,

        Still trying to figure out how to proper constraint my design.

 

        Suppose I have a device (F2) which require a setup time of 2ns and a hold up time of 1ns. Block B is my design on FPGA. F1 and F2 are both driven by the same clock(10 ns), and that there is no skew.  

       

        If I were to constraint output port p, how can I set max output delay and minimum delay? According to technical blog(https://forums.xilinx.com/t5/Technical-Blog/Output-Delay/ba-p/678682), I should set the maximum delay of 2ns to meet device setup time(2ns) and minimum delay of (-1ns).  Am I right?

 

        Also how can I find where the minimum delay lies in the picture below.

 

Thanks! 

 

 

block.jpg

Untitled.png

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Guide
Guide
25,554 Views
Registered: ‎01-23-2009

Sorry sir, I don't understand "coming back" in this context. Could you shade light on this?

max delay which is positive moving to the left (coming "back" from the clock edge)

 

The set_output_delay represents the amount of propagation delay required by the external devices. So, for example, if the clock period is 10, and the set_output_delay -max is 2, then this means that the data must arrive at 8ns; 2ns before the rising edge of the clock. So the set_output_delay represents a time relative to the clock edge, with the positive direction being "earlier" - thus, if you draw it as an arrow in a timing diagram, it is pointing back (toward time 0).
 
Avrum

View solution in original post

Tags (2)
6 Replies
Highlighted
Guide
Guide
18,103 Views
Registered: ‎01-23-2009

First, you say that "F1 and F2 are both driven by the same clock(10 ns), and that there is no skew". This is confusing - your diagram implies that F1 is a flip-flop inside your FPGA which is named block B. Presumably F2 is the external device which has the 2ns SU and 1ns H wrt the clock arriving at F2.

 

My issue is with the definition of the clock in the FPGA - when you say there is no clock skew between F1 and F2 do you really mean there is no skew on the board between the clock arriving at the input pin of the external device (F2) and the input pin of the FPGA (Block B) - this is different than the clock at F1, since the clock goes through a significant path inside the FPGA from the pin of the FPGA to the flip-flop driving an output.

 

Timing constraints specify the characteristics of the system outside the FPGA; therefore a set_output_delay specifies the relationship between an output port of an FPGA and a clock that is connected to an input port of the FPGA; you cannot (well, should not) relate it to an internal clock (i.e. the clock at the flop-flop F1).

 

So assuming the clock between the FPGA and the external device are shared, then your timing diagram and constraints should look like the diagram and constraints below (except that your setup time is 2 whereas the diagram has 1, and your hold has 1 whereas the diagram has 0.5).

 

OutputDelay.jpg

 

Avrum

 

 

 

 

Tags (2)
Highlighted
Contributor
Contributor
18,091 Views
Registered: ‎04-17-2017

Thanks for your great explaination!

 

So can I think of the clock at F1 as a delayed version of system clock? And why is minimum delay a negative value? I initially thought negative value means the signal arriving before clock edge, but it seems to do with the hold time and a hold must be after the clock edge.

 

Chuan

0 Kudos
Highlighted
Guide
Guide
18,087 Views
Registered: ‎01-23-2009

So can I think of the clock at F1 as a delayed version of system clock?

 

From the point of view of timing analysis, you don't need to think about the clock at F1 at all. The tools analyze the complete timing path, which includes:

  - Source Clock Delay: From where the clock is defined (at the port of the design) to the startpoint of the static timing path

      - (this would be the delay to the internal clock, but it is analyzed automatically during static timing analysis)

  - Datapath Delay: From the static timing path startpoint to the endpoint

  - Destination Clock Delay: From where the clock is defined to the endpoint of the static timing path

 

And why is minimum delay a negative value?

 

Setup times are positive before the clock edge (moving toward the left), but hold times are positive after the clock edge (moving toward the right).

 

However, by SDC/XDC definition, the set_output_delay is a min and max delay which is positive moving to the left (coming "back" from the clock edge) - it is the min and max delay required by the receiving device. Therefore, the set_output_delay -min is the negative of the hold time.

 

Avrum

Tags (2)
Highlighted
Contributor
Contributor
17,995 Views
Registered: ‎04-17-2017

Sorry sir, I don't understand "coming back" in this context. Could you shade light on this?

max delay which is positive moving to the left (coming "back" from the clock edge)

0 Kudos
Highlighted
Guide
Guide
25,555 Views
Registered: ‎01-23-2009

Sorry sir, I don't understand "coming back" in this context. Could you shade light on this?

max delay which is positive moving to the left (coming "back" from the clock edge)

 

The set_output_delay represents the amount of propagation delay required by the external devices. So, for example, if the clock period is 10, and the set_output_delay -max is 2, then this means that the data must arrive at 8ns; 2ns before the rising edge of the clock. So the set_output_delay represents a time relative to the clock edge, with the positive direction being "earlier" - thus, if you draw it as an arrow in a timing diagram, it is pointing back (toward time 0).
 
Avrum

View solution in original post

Tags (2)
Highlighted
Observer
Observer
16,121 Views
Registered: ‎12-04-2015

Hi,

the explanation is very good.
Just a question: is the order correct?, I mean for the positive and negative values.

Because according to the "Language Templates" inside Vivado I see the following situation,

which seems to be the opposite:

skew.PNG

And a 2nd question:

You mention that this type of constraint is used for input clk  to output signals. Can I use it for input clk to input signals? I want to use incoming clocks with data signals, all coming from LVDSs...

 

Thanks,

Angelo

 

0 Kudos