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information on speed files

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Visitor
Posts: 6
Registered: ‎02-16-2017

information on speed files

hi all,

 

this might sound very basic, but what are speed files? what information do they carry? and how to view them in vivado?

 

regards,

 

Moderator
Posts: 58
Registered: ‎09-15-2016

Re: information on speed files

@tim2lrn

 

Please refer UG-835, page:-802, and see if it helps.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug835-vivado-tcl-commands.pdf

 

Thanks,

Asit

 

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Visitor
Posts: 6
Registered: ‎02-16-2017

Re: information on speed files

hi @asitm,

 

Yes, thanks that helps somewhat, but i have some clarifications over this.

 

This is more of how to view it in Vivado. So correct me @asitm,

- I understood speed files are provided by xilinx for each device and speed grade. so there is device and its speed grade for each device.

- Speed files contains speed models; so is speed models and speed grade same? which contains timing information for vivado to calculate timings for analysis of the design based on the part selected.

-  Is it only for ultrascale devices? Do we have a location or a separate file for "speed files" or it is just a property?

- Also as per the document you pointed out, I would appreciate if you could please explain the example given in page 804 for this -

 

804.PNG

 

- Do we have any other document which explains about speed files which i missed searching out from the internet?

 

regards,

Moderator
Posts: 58
Registered: ‎09-15-2016

Re: information on speed files

@tim2lrn

 

---This is more of how to view it in Vivado. So correct me @asitm, 

 

Asit>>Along with how to view, if you go deep into the UG you can understand what a speed files provides, what speed models includes, usage of speed models, what are the arguments present in it, etc.

--- Speed files contains speed models; so is speed models and speed grade same? 

Asit>>
In FPGAs represented the time through a look up table but now the speed grade doesn't actually represent a timing path. Xilinx FPGAs higher numbers are faster. Each speed grade increment is ~15% faster than the one before it. So a -5 is 10% faster than a -4 speed grade. 

Speed models include information on the delays in nanoseconds (ns) associated with device resources like BELs and SITEs and routing resources. Speed models are used by the Vivado timing engine to perform analysis of the current design in the context of the target part.

 

---Do we have any other document which explains about speed files which I missed searching out from the internet?

 

Asit>>There are many other (similar) forum posts which you can search for getting more information on Speed files and their usage.

It will be better if you have a timing report of a design, and generated speed models so that you can analyze how the timing delays are fetched from Speed files.

 

Regards,

Asit

 

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Moderator
Posts: 58
Registered: ‎09-15-2016

Re: information on speed files

@tim2lrn

 

--- Also as per the document you pointed out, I would appreciate if you could please explain the example given in page 804 for this 

asitm>> As you must be knowing in FPGA, LUT’s are present. In the example speed model of a LUT is shown which is at site Slice X0Y0 and BEL A6LUT.

I have attached few snapshots for your understanding:-

 

In timing report you can see delays of LUT5 is mentioned, that delay information is fetched from speed model. The same LUT is also marked from device view.


In the example slow_max, fast_min etc. values of the LUT is mentioned.  

[slow_max] is the delay at the slowest process, temperature, voltage combination

[fast_min] is the delay at the fastest process, temperature, voltage combination

[slow_min]: is the shortest delay that can occur in a cell on a die that also has at least one cell at [slow_max]

[fast_max]: is the longest delay that can occur in a cell on a die that also has at least one cell at [fast_min]

 

Refer to below links for getting more information on fast corners and slow corners and speed file:-

 

https://forums.xilinx.com/t5/Timing-Analysis/multi-corner-timing-analysis/td-p/64786

AR#54196, https://www.xilinx.com/support/answers/54196.html

https://forums.xilinx.com/t5/General-Technical-Discussion/What-is-the-mean-of-process-corner/td-p/326871

https://forums.xilinx.com/t5/Timing-Analysis/quot-Slowest-Paths-quot-vs-quot-Fastest-Paths-quot/td-p/66628

 
I hope this will answer all your questions.

 

Thanks,

Asit

 

 

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