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Explorer
Explorer
606 Views
Registered: ‎10-16-2018

my simple design failed to meet the timing

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Hi, 

I am trying to learn the essentials of System Design Timing rules.

So , I made a simple design consisted of Clocking Wizard IP and DDS IP, as shown below :Diagram.JPG

I increased clk_out1 to 400 MHz frequncy, then I ran the Implementation process , but the design failed to meet the timing requirments. As shown below:path1.JPG

There is only one Failing End Point caused by Path 1 .

What I can do in order to fix Path1, in order to meet the Timing? (Without decreasing clk_out1 frequency)

Thanks.

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1 Solution

Accepted Solutions
Historian
Historian
370 Views
Registered: ‎01-23-2009

Re: my simple design failed to meet the timing

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It seems "min_period" the reason for the voilation. What I can do to fix it?

Take a look at the datasheet for the Artix-7 (DS181). 

Specifically look at table 30, under the fMAX_* parameters. These are showing you the maximum operating frequency for the BRAM cells in various operating modes. In the Artix-7 in the -1L speed grade, these are all less than 400MHz - between 300MHz and 388MHz.

This is telling you that the BRAMs will simply not operate (reliably) at 400MHz in this device/speed grade. This can't be "fixed" - if you use BRAMs they need to operate below the fMAX rating for the mode/device/speedgrade you are using.

Avrum

19 Replies
Teacher xilinxacct
Teacher
598 Views
Registered: ‎10-23-2018

Re: my simple design failed to meet the timing

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@ahmed_alfadhel 

Have you already applied path constraints? (One trick I have found, is that when you apply the path constraint, don't be greedy. e.g. ask for just something better (e.g. 1 ns) rather than the full amount needed. Sometimes that is enough to allow a timing closure and sometimes get 'more' than what you need.)

If your design uses LUTs, you 'may' get some benefit of setting the -no_lc flag in the synthesis section. (This may use a few more LUTs, but may improve the routing)

Hope that helps

Explorer
Explorer
587 Views
Registered: ‎10-16-2018

Re: my simple design failed to meet the timing

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Hi @xilinxacct ,


@xilinxacct wrote:

@ahmed_alfadhel 

(One trick I have found, is that when you apply the path constraint, don't be greedy. e.g. ask for just something better (e.g. 1 ns) rather than the full amount needed. Sometimes that is enough to allow a timing closure and sometimes get 'more' than what you need.)


Could you please elaborate more on this .

Thanks

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Xilinx Employee
Xilinx Employee
586 Views
Registered: ‎03-29-2013

Re: my simple design failed to meet the timing

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Have you tried the PerformanceExplore implementation strategy?

Teacher xilinxacct
Teacher
577 Views
Registered: ‎10-23-2018

Re: my simple design failed to meet the timing

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@ahmed_alfadhel 

When you specify the the path constraint, I have found that it is often better to not ask for the full amount of time to but just asking for something better. That can sometime encourage the router to improve the situation, however, when asking for 'all' of the improvement still says it can't resolve it. So, if the current problem path is  X ns too much, apply a constaint that is 1ns better than what it currently is, rather than making the constraint X ns less. It tends to nudge the router in the right direction.

Hope that Helps
If so, Please mark as solution accepted. Kudos also welcomed. :-)

Explorer
Explorer
482 Views
Registered: ‎10-16-2018

Re: my simple design failed to meet the timing

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Hi @frederi ,


@frederi wrote:

Have you tried the PerformanceExplore implementation strategy?


Could you please instructe me about this strategy? Is there a documanetation to read? or an eaxmple to follow?

Thanks

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Scholar watari
Scholar
458 Views
Registered: ‎06-16-2013

Re: my simple design failed to meet the timing

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Hi @ahmed_alfadhel 

 

What target device do you choose ?

Your constraint, 400MHz, and like your design are too fast for almost of all FPGA devices.

 

Best regards,

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Xilinx Employee
Xilinx Employee
450 Views
Registered: ‎03-29-2013

Re: my simple design failed to meet the timing

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Several docs and videos cover it, which can be found via search on xilinx.com or on a web search engine (just make sure to indicate your Vivado release when searching Google, etc...).

Here are 2 links you should take a look at:

- https://www.xilinx.com/video/hardware/vivado-implementation-directives.html

- https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug986-vivado-tutorial-implementation.pdf

 

 

Xilinx Employee
Xilinx Employee
447 Views
Registered: ‎03-29-2013

Re: my simple design failed to meet the timing

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True, although you can hit 700MHz+ on US+ medium speedgrade. Small designs can run faster and take less effort to tune.

In the case of this thread, the violation is 22ps, which should be addressed when increase the tool effort.

There is a pulse-width violation, which could be either min_period, max_period or max_skew. Except for max_skew violations, they usually point to HW running faster than what the datasheet indicates.

Explorer
Explorer
419 Views
Registered: ‎10-16-2018

Re: my simple design failed to meet the timing

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Hi @frederi 

I set Performance_Explore as the implemetation strategy. However, TNS timing is met but the pulse-width still voilated.

Perfomance_Explore.JPG

How to indicate the reason behind the pulse-width voilation? According to your post it could min_period, max_period or max_skew. 

What I can do for min_period or max period?

Thanks

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Xilinx Employee
Xilinx Employee
414 Views
Registered: ‎03-29-2013

Re: my simple design failed to meet the timing

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Go the Timing tab, click on the violation.

You need to view a few basic training videos. Here is where to start: https://www.xilinx.com/products/design-tools/vivado.html#getting_started

 

409 Views
Registered: ‎06-21-2017

Re: my simple design failed to meet the timing

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400MHz will be tough on a -1 Artix.  He might be able to eke out 22pS, but this will be really hard to add to.

Explorer
Explorer
401 Views
Registered: ‎10-16-2018

Re: my simple design failed to meet the timing

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Hi @frederi 

It seems "min_period" the reason for the voilation. What I can do to fix it?

pulse_width_min_period.JPG

Thanks

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Historian
Historian
371 Views
Registered: ‎01-23-2009

Re: my simple design failed to meet the timing

Jump to solution

It seems "min_period" the reason for the voilation. What I can do to fix it?

Take a look at the datasheet for the Artix-7 (DS181). 

Specifically look at table 30, under the fMAX_* parameters. These are showing you the maximum operating frequency for the BRAM cells in various operating modes. In the Artix-7 in the -1L speed grade, these are all less than 400MHz - between 300MHz and 388MHz.

This is telling you that the BRAMs will simply not operate (reliably) at 400MHz in this device/speed grade. This can't be "fixed" - if you use BRAMs they need to operate below the fMAX rating for the mode/device/speedgrade you are using.

Avrum

Scholar drjohnsmith
Scholar
359 Views
Registered: ‎07-09-2009

Re: my simple design failed to meet the timing

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suggest that the Artex DDS running at 400 MHz is to fast for an Artex

select a faster speed part,

You can only push any part so far,
the simpler a design is, the less room you have for "tricks"

Also a lot of your placement is going to be on trying to get the signals to the output, Put some more output registers on the outputs is always a good idea if you trying to get a performance test.

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Scholar drjohnsmith
Scholar
359 Views
Registered: ‎07-09-2009

Re: my simple design failed to meet the timing

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BTW : whats your constraints file look like ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Highlighted
Explorer
Explorer
334 Views
Registered: ‎10-16-2018

Re: my simple design failed to meet the timing

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Hi @drjohnsmith ,

Kindly,

see the attached file . Which is the constraint file that I used for the design .

thanks

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Explorer
Explorer
330 Views
Registered: ‎10-16-2018

Re: my simple design failed to meet the timing

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Hi @drjohnsmith 


@drjohnsmith wrote:

Also a lot of your placement is going to be on trying to get the signals to the output, Put some more output registers on the outputs is always a good idea if you trying to get a performance test.


Could you please instruct me about how to "put some more output registers on the outputs" ?

Thanks.

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Scholar drjohnsmith
Scholar
315 Views
Registered: ‎07-09-2009

Re: my simple design failed to meet the timing

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so your xdc file looks fine,
so the problem is your device just cant run fast enough,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Scholar drjohnsmith
Scholar
315 Views
Registered: ‎07-09-2009

Re: my simple design failed to meet the timing

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sorry , I'd suggest you read up some more,
registers are a basic set of any design,
I cant give complete instructions here,
look in the IP catalogue where you got the DDS etc from,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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