pci express 2.1 vivado 2103.2 Pulse width violation ....

[christian.lambricht]

Hello,

I've implemented a PCI express solution into my design and I have some timing constraint not met (WPWS).

What I want to know is :

What is it exactly ?I didnt find enough info about that?

how I can resolve this?

where is the first step to analyse?

Thanks for your help

Christian Lambricht

[htsvn]

Hi Christian,

Is this a PCIe core generated from Vivado without any modifications?

It looks that there is a maximum skew constraint that is failing.

Did you add any additional constraints in XDC?

--HS

[christian.lambricht · Accepted solution]

Hello,

Thansk a lot for your help.

In fact, I take the XDC from the example design and add some timing constraints....

In the XDC i added constraint "-set_max_delay" between 2 clocks (video clock and userclock) because of FIFO use (clock crossing). To do that I had to create 2 clocks, one is the video clock from a port and the other is a clock from a net (I created this last one because I didn't find the clock name) in Edit Timing Constraints.....

And the issue xas coming from that :)

The solution is to find the userclock name (in my case userclock2) to apply the "-set_max_delay" directive.

Best regards,

Christian Lambricht

[markzak]

I am having the same problem as you did, however i don't know how to fix it.  What exactly did you constrain to remove this?  I read through your solution, but it doesn't seem to apply to me.  I have added a few constraints to the design, but they have nothing to do with the core.

I've tried adding a few from/to Max delay constraints, and they did nothing.  No luck with the group constrains either.  Can someone offer an detailed explanation on how to solve this timing violation??

 Thank you.

Here's the log Post Synth

And Post Implementation

[markzak]

I found my problem.

http://forums.xilinx.com/t5/PCI-Express/PCIe-core-3-0-pulse-width-timing-violation/m-p/411431/thread-id/5063/highlight/false#M5109