cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
chughsumit
Participant
Participant
8,125 Views
Registered: ‎03-04-2015

placement routing delay

Hi,

 

Could you please help let me understand why the placement routing delay path of 3.9ns for path from SLICE_X69Y140 to SLICE_X69Y146 ( looks shorter path in image below as compared to path from SLICX69Y146 to RAM) is taking long routing delay as compared to path SLICEX69Y146 to RAM of 2.174ns.

  SLICE_X69Y140       FDCE (Prop_fdce_C_Q)         0.315   11.043 r falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/vmc_core/uhd_agent/uhd_wr/vuhd_fifoaxiwr/stm_pack_wdata_reg[108]/Q

                        net (fo=4, routed)           3.901   14.943   falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/vmc_core/uhd_agent/uhd_wr/vuhd_fifoaxiwr/stm_pack_wdata[108]

   SLICE_X69Y146       LUT5 (Prop_lut5_I0_O)       0.043   14.986 r falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/vmc_core/uhd_agent/uhd_wr/vuhd_fifoaxiwr/SZLA40_128X128X1CM2b1_mem0_i_29__4/O

                         net (fo=1, routed)           2.174   17.160   falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/memmux/mem_128X256_0/SZLA40_128X128X1CM2b1_mem0/U0/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/dina[36]

   RAMB36_X4Y29         RAMB36E1                                     r

 

 

 

 

 

-----------------------------------------------------------------------------------------------------------------------

 

Slack (VIOLATED) :       -3.219ns (required time - arrival time)

Source:                 falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/vmc_core/uhd_agent/uhd_wr/vuhd_fifoaxiwr/stm_pack_wdata_reg[108]/C

                           (rising edge-triggered cell FDCE clocked by vrx_clk_clk_pll3 {rise@0.000ns fall@1.667ns period=3.333ns})

Destination:           falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/memmux/mem_128X256_0/SZLA40_128X128X1CM2b1_mem0/U0/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/DIBDI[9]

                           (rising edge-triggered cell RAMB36E1 clocked by vrx_fhd_clk_clk_pll3 {rise@0.000ns fall@3.333ns period=6.667ns})

Path Group:             vrx_fhd_clk_clk_pll3

Path Type:             Setup (Max at Slow Process Corner)

Requirement:           3.333ns (vrx_fhd_clk_clk_pll3 rise@6.667ns - vrx_clk_clk_pll3 rise@3.333ns)

Data Path Delay:       6.432ns (logic 0.358ns (5.566%) route 6.074ns (94.434%))

Logic Levels:           1 (LUT5=1)

Clock Path Skew:       0.619ns (DCD - SCD + CPR)

   Destination Clock Delay (DCD):   7.195ns = ( 13.862 - 6.667 )

   Source Clock Delay     (SCD):   7.394ns = ( 10.728 - 3.333 )

   Clock Pessimism Removal (CPR):   0.819ns

Clock Uncertainty:     0.196ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE

   Total System Jitter     (TSJ):   0.071ns

   Discrete Jitter         (DJ):   0.135ns

   Phase Error             (PE):   0.120ns

 

   Location             Delay type               Incr(ns) Path(ns)   Netlist Resource(s)

-------------------------------------------------------------------   -------------------

                        (clock vrx_clk_clk_pll3 rise edge)

                                                     3.333     3.333 r

   AA8                                               0.000     3.333 r VB1_FIXEDCLKREF0p (IN)

                         net (fo=0)                   0.000     3.333   VB1_FIXEDCLKREF0p

   AA8                 IBUF (Prop_ibuf_I_O)         0.000     3.333 r VB1_FIXEDCLKREF0p_IBUF_inst/O

                         net (fo=1, routed)           0.000     3.334   pqasic_tpv/gaboon/U_3/VB1_FIXEDCLKREF0p_IBUF

   IBUFDS_GTE2_X0Y2     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)

                                                     2.355     5.689 r pqasic_tpv/gaboon/U_3/refclock_buffer/O

                         net (fo=1, routed)           1.243    6.932   pqasic_tpv/gaboon/U_3/refclock_buffer_n_2

   BUFGCTRL_X0Y13       BUFG (Prop_bufg_I_O)         0.093     7.025 r pqasic_tpv/gaboon/U_3/clkf_buf/O

                         net (fo=1, routed)           1.441     8.466   pqasic_tpv/gaboon/clocks/pll4/inst/clk_in_vbotx_148

   MMCME2_ADV_X0Y2     MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT4)

                                                     -3.018    5.448 r pqasic_tpv/gaboon/clocks/pll4/inst/mmcm_adv_inst/CLKOUT4

                         net (fo=1, routed)           1.484     6.932   pqasic_tpv/gaboon/clocks/pll4/inst/vtx_stream_clk_clk_pll4

   BUFGCTRL_X0Y9       BUFG (Prop_bufg_I_O)         0.093     7.025 r pqasic_tpv/gaboon/clocks/pll4/inst/clkout5_buf/O

                         net (fo=1770, routed)       1.913     8.938   pqasic_tpv/gaboon/clocks/pll3/inst/clk_in_pll4_75

   MMCME2_ADV_X1Y6     MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT0)

                                                     -4.189     4.749 r pqasic_tpv/gaboon/clocks/pll3/inst/mmcm_adv_inst/CLKOUT0

                         net (fo=1, routed)           2.185     6.934   pqasic_tpv/gaboon/clocks/pll3/inst/vrx_clk_clk_pll3

   BUFGCTRL_X0Y27       BUFG (Prop_bufg_I_O)         0.093     7.027 r pqasic_tpv/gaboon/clocks/pll3/inst/clkout1_buf/O

                         net (fo=9, routed)           1.759     8.786   falcon_fpga_top/falcon/falcon_coremux/falcon_core/scm/vrx_clk_vpu1_gater/cgcelln/fpga_vidclk_sip_vrx_clk

      BUFGCTRL_X0Y27       BUFG (Prop_bufg_I_O)         0.093     7.027 r pqasic_tpv/gaboon/clocks/pll3/inst/clkout1_buf/O

                         net (fo=9, routed)           1.759     8.786   falcon_fpga_top/falcon/falcon_coremux/falcon_core/scm/vrx_clk_vpu1_gater/cgcelln/fpga_vidclk_sip_vrx_clk

   SLICE_X67Y218       LUT2 (Prop_lut2_I0_O)       0.053     8.839 r falcon_fpga_top/falcon/falcon_coremux/falcon_core/scm/vrx_clk_vpu1_gater/cgcelln/scm_vrx_clk_vpu1_INST_0/O

                         net (fo=4042, routed)       1.889   10.728   falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/vmc_core/uhd_agent/uhd_wr/vuhd_fifoaxiwr/scm_vrx_clk_vpu1

   SLICE_X69Y140       FDCE                                         r falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/vmc_core/uhd_agent/uhd_wr/vuhd_fifoaxiwr/stm_pack_wdata_reg[108]/C

-------------------------------------------------------------------   -------------------

   SLICE_X69Y140       FDCE (Prop_fdce_C_Q)         0.315   11.043 r falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/vmc_core/uhd_agent/uhd_wr/vuhd_fifoaxiwr/stm_pack_wdata_reg[108]/Q

                        net (fo=4, routed)           3.901   14.943   falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/vmc_core/uhd_agent/uhd_wr/vuhd_fifoaxiwr/stm_pack_wdata[108]

   SLICE_X69Y146       LUT5 (Prop_lut5_I0_O)       0.043   14.986 r falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/vmc_core/uhd_agent/uhd_wr/vuhd_fifoaxiwr/SZLA40_128X128X1CM2b1_mem0_i_29__4/O

                         net (fo=1, routed)           2.174   17.160   falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/memmux/mem_128X256_0/SZLA40_128X128X1CM2b1_mem0/U0/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/dina[36]

   RAMB36_X4Y29         RAMB36E1                                     r falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/memmux/mem_128X256_0/SZLA40_128X128X1CM2b1_mem0/U0/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/DIBDI[9]

-------------------------------------------------------------------   -------------------

 

                         (clock vrx_fhd_clk_clk_pll3 rise edge)

                                                     6.667     6.667 r

   AA8                                              0.000     6.667 r VB1_FIXEDCLKREF0p (IN)

                         net (fo=0)                   0.000     6.667   VB1_FIXEDCLKREF0p

   AA8                 IBUF (Prop_ibuf_I_O)         0.000     6.667 r VB1_FIXEDCLKREF0p_IBUF_inst/O

                         net (fo=1, routed)           0.000     6.667   pqasic_tpv/gaboon/U_3/VB1_FIXEDCLKREF0p_IBUF

   IBUFDS_GTE2_X0Y2     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)

                                                     1.418     8.085 r pqasic_tpv/gaboon/U_3/refclock_buffer/O

                         net (fo=1, routed)           1.179     9.264   pqasic_tpv/gaboon/U_3/refclock_buffer_n_2

   BUFGCTRL_X0Y13       BUFG (Prop_bufg_I_O)         0.083     9.347 r pqasic_tpv/gaboon/U_3/clkf_buf/O

                         net (fo=1, routed)           1.285   10.632   pqasic_tpv/gaboon/clocks/pll4/inst/clk_in_vbotx_148

   MMCME2_ADV_X0Y2     MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT4)

                                                     -2.735     7.897 r pqasic_tpv/gaboon/clocks/pll4/inst/mmcm_adv_inst/CLKOUT4

                         net (fo=1, routed)           1.367     9.264   pqasic_tpv/gaboon/clocks/pll4/inst/vtx_stream_clk_clk_pll4

   BUFGCTRL_X0Y9       BUFG (Prop_bufg_I_O)         0.083     9.347 r pqasic_tpv/gaboon/clocks/pll4/inst/clkout5_buf/O

                         net (fo=1770, routed)       1.660   11.007   pqasic_tpv/gaboon/clocks/pll3/inst/clk_in_pll4_75

   MMCME2_ADV_X1Y6     MMCME2_ADV (Prop_mmcme2_adv_CLKIN2_CLKOUT1)

                                                     -3.744     7.263 r pqasic_tpv/gaboon/clocks/pll3/inst/mmcm_adv_inst/CLKOUT1

                         net (fo=1, routed)           2.003     9.266   pqasic_tpv/gaboon/clocks/pll3/inst/vrx_fhd_clk_clk_pll3

   BUFGCTRL_X0Y28       BUFG (Prop_bufg_I_O)         0.083     9.349 r pqasic_tpv/gaboon/clocks/pll3/inst/clkout2_buf/O

                         net (fo=5, routed)           1.570   10.919   falcon_fpga_top/falcon/falcon_coremux/falcon_core/scm/vrx_fhd_clk_vpu1_gater/cgcelln/fpga_vidclk_sip_vrx_fhd_clk

   SLICE_X67Y251       LUT2 (Prop_lut2_I1_O)       0.041   10.960 r falcon_fpga_top/falcon/falcon_coremux/falcon_core/scm/vrx_fhd_clk_vpu1_gater/cgcelln/scm_vrx_fhd_clk_vpu1_INST_0/O

                         net (fo=12764, routed)       1.773   12.733   falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/vmc_core/riu/scm_vrx_fhd_clk_vpu1

   SLICE_X50Y141       LUT3 (Prop_lut3_I2_O)       0.109   12.842 r falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/vmc_core/riu/SZLA40_128X128X1CM2b1_mem0_i_1__0/O

                        net (fo=16, routed)         1.019   13.862   falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/memmux/mem_128X256_0/SZLA40_128X128X1CM2b1_mem0/U0/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/clka

   RAMB36_X4Y29         RAMB36E1                                     r falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/memmux/mem_128X256_0/SZLA40_128X128X1CM2b1_mem0/U0/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/CLKBWRCLK

                         clock pessimism             0.819   14.681

                         clock uncertainty           -0.196   14.484

   RAMB36_X4Y29         RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_DIBDI[9])

                                                     -0.543   13.941   falcon_fpga_top/falcon/falcon_coremux/falcon_core/vpu1_system/vmc/memmux/mem_128X256_0/SZLA40_128X128X1CM2b1_mem0/U0/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram

-------------------------------------------------------------------

                         required time                        13.941

                         arrival time                         -17.160

-------------------------------------------------------------------

                         slack                                 -3.219

 

photo1.JPG

0 Kudos
2 Replies
aher
Xilinx Employee
Xilinx Employee
8,100 Views
Registered: ‎07-21-2014

Hi,

 

you can turn on "Routing Resources" (Highligheted Yellow) option. 

You can then observe the actual routing of both these nets which may explain why shorter path has longer routing delay.

 

Capture.PNG

Thanks,

Shreyas

----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
Give Kudos (star provided in right) to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
yashp
Moderator
Moderator
8,075 Views
Registered: ‎01-16-2013

Hi,

This happens due to congestion in routing.
The image just shows the placement of two component and that they are connected.

As you can see the white like is crossing blue elements its not possible practically. Tool is using long route to connect and that's reason delay is high.

You can floorplan your design for better performance.

Thanks,
Yash
0 Kudos