UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor cds_team
Visitor
18,777 Views
Registered: ‎01-29-2010

recommented timing constraint for differential clock signal / coding style of manually inserted global clock buffer

Jump to solution

Hello!

 

what is the recommended way to apply a timing constraint on a differential clock signal?

 

example module:

module designTop (
input reset_N,
input fpgaClk200MHzP,
input fpgaClk200MHzN,
);
// 200 MHz clock
wire fpgaClk200MHz_BUFG;
(* clock_signal = "yes"*) wire fpgaClk200MHz;

IBUFGDS_LVDS_25 CLKLVDS (.I(fpgaClk200MHzP), .IB(fpgaClk200MHzN), .O(fpgaClk200MHz_BUFG));
BUFG CLK200MHZ_BUFG (.I(fpgaClk200MHz_BUFG), .O(fpgaClk200MHz));

always@(posedge fpgaClk200MHz, negedge reset_N) begin
if (!reset_N) begin
...
end
end
endmodule

1.) how would you recommend to apply the timing constraint in the UCF file:

     a.) timing constraint like this:

 

NET "fpgaClk200MHzN" TNM_NET = "fpgaClk200MHzN";
NET "fpgaClk200MHzP" TNM_NET = "fpgaClk200MHzP";
TIMESPEC "TS_fpgaClk200MHzN" = PERIOD "fpgaClk200MHzN" 5 ns LOW 50%;
TIMESPEC "TS_fpgaClk200MHzP" = PERIOD "fpgaClk200MHzP" "TS_fpgaClk200MHzN" HIGH 50%;

 

     b.)

 

NET "fpgaClk200MHzN" TNM_NET = "fpgaClk200MHzN";
NET "fpgaClk200MHzP" TNM_NET = "fpgaClk200MHzP";
TIMESPEC "TS_fpgaClk200MHzN" = PERIOD "fpgaClk200MHzN" 5 ns LOW 50%;
TIMESPEC "TS_fpgaClk200MHzP" = PERIOD "fpgaClk200MHzP" 5 ns HIGH 50%;

 or c.)

 

NET "fpgaClk200MHz" TNM_NET = tnm_fpgaClk200MHz ;
TIMESPEC TS_fpgaClk200MHz = PERIOD tnm_fpgaClk200MHz 5ns HIGH 50%;

 

 

 

2.) is it necessary to define the clock_signal attribute of fpgaClk200Mhz if the global clock buffer is inserted manually?

 

Thank you very much,

 

                                       cds.

 

 

Message Edited by cds_team on 03-16-2010 07:34 AM
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
22,725 Views
Registered: ‎01-03-2008

Re: recommented timing constraint for differential clock signal / coding style of manually inserted global clock buffer

Jump to solution

The answer record said to apply the period constraint to the P side of the differential input buffer which is exactly what the previous poster did.

NET "fpgaClk200MHzP" TNM_NET = "fpgaClk200MHzP";
TIMESPEC "TS_fpgaClk200MHzP" = PERIOD "fpgaClk200MHzP" 5 ns HIGH 50%;

or more simply

 

 NET "fpgaClk200MHzP" PERIOD = 5 nS;

 

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
8 Replies
Highlighted
Xilinx Employee
Xilinx Employee
18,772 Views
Registered: ‎08-02-2007

Re: recommented timing constraint for differential clock signal / coding style of manually inserted global clock buffer

Jump to solution

Hi,

 

This is the recommended way to constrain Differential pair.

 

http://www.xilinx.com/support/answers/15833.htm

 

Thnx

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Visitor cds_team
Visitor
18,762 Views
Registered: ‎01-29-2010

Re: recommented timing constraint for differential clock signal / coding style of manually inserted global clock buffer

Jump to solution

Hello!

 

Thx for your reply!

 

Just to share my experiences...

 

The following code resulted to work best in my case (especially, in this way I didn't get any problems with the subsequent DCMs, which are included in the real code..)

 

I decided not to instantiate the global clock buffer (resulting in the following  code:)

module designTop (
input reset_N,
input fpgaClk200MHzP,
input fpgaClk200MHzN
);
// 200 MHz clock
(* clock_signal = "yes"*) wire fpgaClk200MHz;

IBUFGDS_LVDS_25 CLKLVDS (.I(fpgaClk200MHzP), .IB(fpgaClk200MHzN), .O(fpgaClk200MHz));

always@(posedge fpgaClk200MHz, negedge reset_N) begin
if (!reset_N) begin
...
end
end
endmodule

 

and to apply following timing constraint:

 

NET "fpgaClk200MHzP" TNM_NET = "fpgaClk200MHzP";
TIMESPEC "TS_fpgaClk200MHzP" = PERIOD "fpgaClk200MHzP" 5 ns HIGH 50%;

with following pin location constraints

 

NET "fpgaClk200MHzP" LOC = H19 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE ; NET "fpgaClk200MHzN" LOC = H20 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE ;

 

 

I just want to mention, that there is no example of a PERIOD constraint of a differential pair input in ug612.pdf (nor in the constraints guide)! (At least I didn't find one..)

 

In AR#15833, the solution is to place a TNM_NET PERIOD on the DIFF clock input... How would such a constraint look like, or is this exactly what the posted code does? (Please forgive me this kind of questions, but I'm a newbie to constraints... (I've read the user guides about constraints and timing constraints, but as already mentioned, I didn't find any detailed information on differential inputs...))

 

Thx again and best Regards,

 

                      cds.

Message Edited by cds_team on 03-16-2010 10:01 AM
Message Edited by cds_team on 03-16-2010 10:02 AM
Message Edited by cds_team on 03-16-2010 10:06 AM
Explorer
Explorer
17,632 Views
Registered: ‎11-27-2008

Re: recommented timing constraint for differential clock signal / coding style of manually inserted global clock buffer

Jump to solution

I'd like a better answer to this question as well. The answer record referred to has less detail than the original question that was asked by the poster. The question was very clearly spelled out with 3 different examples given. Please, just tell us which one is correct.

 

The Constraints User Guide should also be updated with specific examples.

 

Regards,

Dan

 

0 Kudos
Xilinx Employee
Xilinx Employee
22,726 Views
Registered: ‎01-03-2008

Re: recommented timing constraint for differential clock signal / coding style of manually inserted global clock buffer

Jump to solution

The answer record said to apply the period constraint to the P side of the differential input buffer which is exactly what the previous poster did.

NET "fpgaClk200MHzP" TNM_NET = "fpgaClk200MHzP";
TIMESPEC "TS_fpgaClk200MHzP" = PERIOD "fpgaClk200MHzP" 5 ns HIGH 50%;

or more simply

 

 NET "fpgaClk200MHzP" PERIOD = 5 nS;

 

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
Explorer
Explorer
17,618 Views
Registered: ‎11-27-2008

Re: recommented timing constraint for differential clock signal / coding style of manually inserted global clock buffer

Jump to solution

Thanks much for the clarification.

 

Regards,

Dan

 

0 Kudos
Xilinx Employee
Xilinx Employee
17,596 Views
Registered: ‎11-06-2007

Re: recommented timing constraint for differential clock signal / coding style of manually inserted global clock buffer

Jump to solution
I would recommend using the TNM_NET syntax as there is a known issue with the NET syntax. PLease see the following:
http://www.xilinx.com/support/answers/17063.htm

I'll also mark this tread as solved from your response on 23 Nov.
0 Kudos
Visitor jwilkinson7
Visitor
13,143 Views
Registered: ‎11-20-2008

Re: recommented timing constraint for differential clock signal / coding style of manually inserted global clock buffer

Jump to solution

mcgett wrote:

The answer record said to apply the period constraint to the P side of the differential input buffer which is exactly what the previous poster did.

NET "fpgaClk200MHzP" TNM_NET = "fpgaClk200MHzP";
TIMESPEC "TS_fpgaClk200MHzP" = PERIOD "fpgaClk200MHzP" 5 ns HIGH 50%;

or more simply

 

 NET "fpgaClk200MHzP" PERIOD = 5 nS;

 


Perhaps the referenced AR # 15833 wasn't what you meant, or perhaps it changed since this original conversation (2010), but now it doesn't say anything of the sort.

 

Is there some other AR you meant? 

 

Also, AR 15833 is answering a specific question from someone who wants the N input to drive the clk analysis, but what about normal uses? (where P is the main phase you want)

 

Do you add PERIOD constraints to both P and N inputs?  Or just P?

 

If so, how?  Syntax examples would be useful, especially if you are constraining both P and N. .

 

As others here pointed out, the xilinx docs have very little on constraining differential inputs.

 

thanks,

jeff

--
jeff wilkinson
jwilkinson@mail.com
0 Kudos
Xilinx Employee
Xilinx Employee
13,127 Views
Registered: ‎07-16-2008

Re: recommented timing constraint for differential clock signal / coding style of manually inserted global clock buffer

Jump to solution

You can add PERIOD constraint to just the _P side of diff pair.

e.g.

NET "clk_p" TNM_NET = clk;

TIMESPEC TS_clk = PERIOD "clk" 10 ns HIGH 50%;

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos