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9,819 Views
Registered: ‎07-15-2015

set_false_path necessary for loopback path on bidirectional port?

Using an Artix-7, have a bidirectional bus. Call it bi_port1.

 

In input mode, there is a register capturing the input data. Call this in_reg1.

 

Similarly, there is an output register launching data through a tri-stateable OBUFT out when enabled. Call it out_reg1.

 

The real paths of interest are

bi_port1 --> in_reg1/D (in input mode)

and

out_reg1/C (through Q) --> bi_port1 (in output mode)

 

In other tools and devices I've worked with, there is typically an internal loop that is NOT of interest,

from out_reg1/Q --> through the OBUFT --> through the IBUF --> back to in_reg1/D

that would be declared a false_path.

 

Interestingly enough, I cannot see this timing path in the current Artix-7 design (with Vivado 2015.4) regardless of what I do!

 

Originally there were set_max_delay -data_path only constraints on the logic in both directions:

bi_port1 --> in_reg1/D (in input mode was 5ns)

and

out_reg1/C --> bi_port1 (in output mode was 5ns)

 

report_timing and get_timing_paths -through OBUFT or -through IBUF will report the normal paths, but not the loopback one.

 

The individual timing arcs through provide cell delay values through OBUFT and IBUF in the individual reports, so set_disable_timing could not have been applied to those elements.

 

Knowing that set_max_delay causes path segmentation, I did a reset_timing/update_timing to clear out the constraints, and only applied the relevant top-level create_clock commands. Run the timing reports again, and no loopback path found.

 

I've done reset_timing/update_timing, set_max_delay -from -to these points, confirmed Vivado accepted the command, redone the report_timing command and gotten more of the same: INFO: [Timing 38-72] No paths found.

 

It seems Vivado is doing something magical under the hood to prevent this loop from being analyzed, and I'll be happy to let it as long as I can find something documenting what's going in.

 

Does anyone know?

 

Many thanks,

 

--jmj

 

 

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14 Replies
Xilinx Employee
Xilinx Employee
9,762 Views
Registered: ‎05-07-2015

Re: set_false_path necessary for loopback path on bidirectional port?

HI john.johnson2@rockwellcollins.com

 

That is strange. As far as I know, Vivado too by itself should not ignore loopback path automatically. Atleast , it does not happen in 2015.2.
refer to this post, where the user was advised to use false path on loopback path in Vivado 2015.2
https://forums.xilinx.com/t5/Timing-Analysis/Why-is-IN-and-OUT-of-IOBUFDS-reported-on-one-timing-path/m-p/644240#M8336

 

Can you just try  " report_timing -through <OBUFT> -through<IBUF> "  and  see if no paths are reported?

 

Note: Just a hunch,  this path might  also get ignored  even without any explicit false path if you are sending out the output data with one clock and capturing input data with another  and have declared those two clock domains as -asynchronous.

 

Thanks
Bharath
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9,708 Views
Registered: ‎07-15-2015

Re: set_false_path necessary for loopback path on bidirectional port?

Thanks Barath,

 

Your link looks pretty much like the situation I have, except for single-ended CMOS instead of LVDS.

 

Still with 2015.4:

report_timing -through <OBUFT> -through<IBUF>

returns no paths, and both registers are definitely in the same clock domain.

 

I have re-created a very simple, stripped down example (hopefully a correct reproduction). VHDL and XDC attached; schematic with "secret path" appended below.

 

Source file iob_hack.vhd is attached.

Only constraint is

create_clock -period 10.0 -name clk [get_ports clk]

which should definitely cover a path from

out_q_reg, through OBUFT, through IBUF, through a LUT, ending at inp_q_reg.

 

report_timing -max_paths 16 -through [get_pins biport_IOBUF_inst/OBUFT/I] -path_type summary

returns only one path,starting at out_q_reg/C and ending at biport.

(infinite slack since there is no constraint on the port)

 

report_timing -max_paths 16 -through [get_pins biport_IOBUF_inst/IBUF/*] -path_type summary

returns only one path, starting at biport and ending at inp_q_reg/D

(infinite slack since there is no constraint on the port)

 

And the following commands returns no path:

get_timing_paths -max_paths 16 -through [get_pins biport_IOBUF_inst/OBUFT/I] -through [get_pins biport_IOBUF_inst/IBUF/*]
WARNING: [Vivado 12-975] No timing paths matched 'get_timing_paths...

 

report_timing -max_paths 16 -through [get_pins biport_IOBUF_inst/OBUFT/I] -through [get_pins biport_IOBUF_inst/IBUF/*]
INFO: [Timing 38-78] ReportTimingParams: -through_pins -max_paths 16 -nworst 1 -delay_type max -sort_by slack.
INFO: [Timing 38-72] No paths found.

 

I will repeat with 2015.2 if still installed on my network.

 

Thanks again!

 

 

 

path_sch.JPG

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9,702 Views
Registered: ‎07-15-2015

Re: set_false_path necessary for loopback path on bidirectional port?

Well, I no longer have 2014.2 on the network, but got the same result with 2015.3 and 2014.4

 

Taking a stab at the 2104.4 version (simplified design example attached above), ran report_disable_timing and got the following:

 

-------------------------------------------------------------------------------------------------------
Cell or Port From To Reason
-------------------------------------------------------------------------------------------------------
biport_IOBUF_inst/OBUFT/O biport_IOBUF_inst/IBUF/I constraint
biport_IOBUF_inst_i_1 I0 O constant negative_unate
inp_q_i_1 I1 O constant positive_unate
inp_q_i_1 I2 O constant positive_unate
inp_q_reg C CE constant
inp_q_reg C CE constant
inp_q_reg C R constant
inp_q_reg C R constant
out_q_reg C CE constant
out_q_reg C CE constant
out_q_reg C R constant
out_q_reg C R constant

 

So there's the smoking gun! Because name_IOBUF_inst is a hierarchical cell, Xilinx is able to break that path inside the cell.

 

The help command for report_disable timing also states:

 

The various reasons for exclusion are as follows:

* constraint - set_disable_timing constraint is specified

* constant - Logic constant

* loop - Breaks a logic loop

* bidirect instance path - Feedback path through bidirectional instances

* bidirect net path - Feedback path on nets with bidirectional pins

 

That brings up the question though: Is there a way to re-enable a disabled timing arc?

 

set_disable_timing does not offer a "-false" switch or list any related commands that do.

 

Thanks again!

 

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9,701 Views
Registered: ‎07-15-2015

Re: set_false_path necessary for loopback path on bidirectional port?

Meant to say I no longer have 2015.2 (typed 2014.2), and apologize for misspelling your name in previous post...

 

... and also inquire as to whether the IOBUFDS cell in your linked post also gets the automatic set_disable_timing attribute on that arc...

 

Being different hierarchical cell types in the Vivado library, the single-ended version might have gotten it, whereas the LVDS version did not. That could explain why you saw it in 2015.2, but I did not in 2014.4 or 2015.4

 

 

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9,697 Views
Registered: ‎07-15-2015

Re: set_false_path necessary for loopback path on bidirectional port?

I had to create this image for internal documentation anyway, so pasting it here for clarity:

 

bidir_set_disable_timing.JPG

Xilinx Employee
Xilinx Employee
9,669 Views
Registered: ‎05-07-2015

Re: set_false_path necessary for loopback path on bidirectional port?

HI john.johnson2@rockwellcollins.com

 

Thats true . The tool is disabling the internal timing arc to IOBUF.(which is indeed a good thing).

 

"That brings up the question though: Is there a way to re-enable a disabled timing arc?"

Any reason why do you need to do that?

Thanks
Bharath
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9,622 Views
Registered: ‎07-15-2015

Re: set_false_path necessary for loopback path on bidirectional port?

>> "That brings up the question though: Is there a way to re-enable a disabled timing arc?"

> Any reason why do you need to do that?

 

Because there might other situations or scenarios where I want to time that path, and possibly other paths that I didn't know the tool disabled.

 

Also, there are scenarios where I could be doing timing analysis or report generation, need to disable an arc (perhaps one of my own, not necessarily inside a Xilinx cell) temporarily, then re-enable it and continue. In order to do so, I would have to do a complete reset_timing and re-read my constraints file.

 

FWIW, the Synopsys version of set_disable_timing includes a "-restore" switch.  :)

 

 

9,618 Views
Registered: ‎07-15-2015

Re: set_false_path necessary for loopback path on bidirectional port?

> The tool is disabling the internal timing arc to IOBUF.(which is indeed a good thing).

 

I guess I can't completely agree that it's a good thing, if the tool doesn't tell me about it by default or give me a way to override it.

 

It's a really weird scenario I just dreamed up, but if there were a case where no external driver is connected to the bidirectional port, and no pull-ups or pull-downs, you might want to be able to set a value on the input register by writing to it through that output register.

 

Or perhaps to monitor that the input path is not getting shorted high or low or otherwise manipulated externally -- you could write to the output register and expect to see the same value on your input register; that would require a timed path.

 

It should not be permanently disabled beyond the user's control and without warning.

 

As a side note, I have not tested it, but wondered: Instead of letting Vivado infer the hierarchical IOBUF cell which comes with the disabled timing arcs, maybe the designer could instantiate OBUFT and IBUF directly. In doing so, the arc may not be disabled. (Anyone tried?)

 

 

Xilinx Employee
Xilinx Employee
9,613 Views
Registered: ‎05-07-2015

Re: set_false_path necessary for loopback path on bidirectional port?

HI john.johnson2@rockwellcollins.com

 

I somehow preempted that you would come up with such a use case :)
But I have not  personally come across any  situation like this >> "but if there were a case where no external driver is connected to the bidirectional port,".

 

>>"maybe the designer could instantiate OBUFT and IBUF directly. In doing so, the arc may not be disabled. (Anyone tried?)"
Got the same hunch and tried it immediately after you sent the hdl file. No , the internal timing arc is automatically disabled even with IOBUF instantiation.

Thanks
Bharath
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Historian
Historian
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Registered: ‎01-23-2009

Re: set_false_path necessary for loopback path on bidirectional port?

Does anyone know where teh set_disable_timing on the OBUFT to IBUF path is coming from? I don't think Vivado puts this in "under the hood" -  would expect that it would have to come in from some .XDC file.

 

I expect that somewhere in the design process, Vivado is automatically generating an XDC file with this constraint and applying it to the cell - if so, I want to know where... (Although the report_disable_timing does seem to imply it is "automatic"). If so, I can find no configuration command that might disable this behaviour (like config_timing_analysis - it has the ability to enable/disable other timing arcs, but not this one).

 

I agree with john.johnson2@rockwellcollins.com - I don't think the tools should automatically be disabling this arc. The main reason for this is that it is unexpected; as designers we expect this path to exist, and, if necessary, should disable it with a constraint (usually a set_false_path -through).

 

On a more concrete example, this path can actually be critical. For example, I2C does actually sense the result of its own output as modified by the external device (look at "clock stretching" in I2C). In this scenario, this path is real, and having it disabled potentially leads to an underconstrained design.

 

Avrum

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Xilinx Employee
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Registered: ‎05-07-2015

Re: set_false_path necessary for loopback path on bidirectional port?

HI @avrumw

 

Thank you very much for the I2C example :)

and yes! it does make sense to analyse timing arc by default leaving it to the designer to define it as  false path if needed.
In fact, I was under the impression that the tool analyses this path  by default till now.

Thanks
Bharath
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8,043 Views
Registered: ‎07-15-2015

Re: set_false_path necessary for loopback path on bidirectional port?

Also chiming in with thanks to Bharath for the follow-up and testing the separate instantiations, and to Avrum for the concrete example.

 

I also had something like an I2C port in mind, have since I've never actually had to design or constrain one, couldn't address it so concretely.

 

I do find it interesting that the LVDS version of IOBUF does not disable this timing arc, and hopefully they won't. That was maybe just a little too helpful on the single-ended version.  ;)

 

As far as direct instantiation having the arc disabled, I assume that Vivado is just implementing it as the hierarchical IOBUF and not as two distinct components.

 

With two distinct components, you couldn't disable the arc from one path and preserve the other, unless the tool eventually makes it two separate nets and applies set_disable_timing to the net between them (or does something really stupid like inserting another buffer just to make two unique nets, one with the attribute and one without).

 

Anyway, it's good to understand the behavior better as we do now, and maybe Xilinx will undo the automatic setting for us (and also give us a way to restore other disabled arcs.)

 

I will put a link to this thread in the related thread Bharath pointed us to.

 

Thanks again!

 

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Xilinx Employee
Xilinx Employee
8,017 Views
Registered: ‎05-07-2015

Re: set_false_path necessary for loopback path on bidirectional port?

HI john.johnson2@rockwellcollins.com

 

Timing arcs  are being ignored  with IOBUFDS (implemented prject archive of 2015.4 attached) as well.  Both in 2015.4 and 2015.2 version.

This makes me wonder how @legendbb got this timing arc to be analysed in 2015.2. I  will send a message  asking for his/her comment on this.

Capture.JPG

Thanks
Bharath
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Visitor dbrent
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Registered: ‎02-05-2019

Re: set_false_path necessary for loopback path on bidirectional port?

Is it possible to enable OBUFT/O to IBUF/I paths that are automatically disabled by Vivado as discussed in this thread?

My application has internal test logic that drives bidirectional I/Os that are inputs to the normal functional logic. This enables the test logic to detect stuck/shorted inputs. The output registers of the test logic and the input registers of the normal logic are placed in the IOBs and are clocked by separate 100MHz clock phases but Vivado will not analyze the path between them because of the automatic (set_disable_timing?) constraints imposed on OBUFT/O to IBUF/I paths/arcs by Vivado.

Thanks,

Dave Brent

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