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geschema1

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10-30-2017 03:20 AM

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12-28-2011

What kind of jitter does the set_input_jitter command expect? RMS or peak-peak?

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ashishd

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10-30-2017 04:49 AM

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Hi @geschema1,

This thread can be helpful

Regards,

Ashish

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ashishd

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10-30-2017 04:49 AM

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Hi @geschema1,

This thread can be helpful

Regards,

Ashish

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Give Kudos to a post which you think is helpful and reply oriented.

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Ashish

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Thanks @ashishd. So it appears that set_input_jitter expects a peak-to-peak (called cycle-cycle jitter in the thread) value for the specified jitter. It would be useful to add that information to manual page for that command.

geschema1

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10-30-2017 05:10 AM

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ashishd

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10-30-2017 05:44 AM - edited 10-30-2017 05:44 AM

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Hi @geschema1,

Page #1542 from below UG gives you an description about this command set_input_jitter. There it has given an idea about jitter mentioning 'Input jitter is the difference between successive clock edges due to variation from the ideal arrival times.'

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug835-vivado-tcl-commands.pdf

Close the thread if this information has addressed your question, by marking helpful post as solution.

Regards,

Ashish

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geschema1

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10-30-2017 05:56 AM

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Hi @ashishd,

the remaining question, of course, is how to compute the value that set_input_jitter expects from, say an oscillator's RMS jitter specification. Assuming that my oscillator has 10 ps period jitter RMS, what conversion factor should I use to convert that value to a peak-peak value for set_input_jitter?

Thanks,

Guy.

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austin

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10-30-2017 07:18 AM

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02-27-2008

RMS -> P=P,

The generally accepted value is 14. So 10 rms is 140 P-P.

That is almost certainly a terribly cheap oscillator. 45 ps P-P is common, with 25 ps P-P being a number for especially low jitter oscillators.

Peak to peak is defined as the worst case over any number of cycles, deviation from a perfect clock. It is not one cycle to the next cycle.

Think of it this way: your timing constraint specifies the minimum period. What if that period is 150 ps shorter on one clock cycle? That would mean you really need to have a time constraint tighter by 150 ps. The jitter is 300 ps P-P, and half that, implies the shortest period of the clock.

The tools take the clock jitter, and system jitter (something you need to review and set to something other than the default). All jitter in the tools are P-P. Jitter summation uses the square root of the sum of the squares (quadratic sum) as that is how it is done for adding P-P values. RMS would use simple addition, P-P does not. RMS really has no meaning in the synchronous digital system.

Austin Lesea

Principal Engineer

Xilinx San Jose

Principal Engineer

Xilinx San Jose

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geschema1

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10-30-2017 11:43 AM

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Thanks @austin, that's a great answer.

At a conversion factor of 14, the remaining probability of error is something like 1e-12. And this is so low that you're assuming that the corresponding worst-case deviation will never be exceeded, right?

Guy Eschemann

FPGA Consultant

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austin

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10-30-2017 12:52 PM

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Registered:
02-27-2008

Yes, and no,

The factor assumes gaussian distribution, which only covers jitter due to noise-like sources. Most jitter is due to deterministic signals (cross talk, power supply ripple). So, the right way to do this is to measure it on your board, and look at it.

Until you actually look at it, you have no idea what is going on.

One uses the rule of thumb numbers to start with, and then goes back and verifies everything.

Austin Lesea

Principal Engineer

Xilinx San Jose

Principal Engineer

Xilinx San Jose