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Voyager
Voyager
1,506 Views
Registered: ‎05-14-2017

set_output _delay constraint clarification

How would one define the proper output delay constraint between a rising clock and an output signal properly.

For example<, if I have two signals leaving the FPGA, "CLOCK" and "MOSI" and I want the MOSI to be DELAY 5ns from the "CLOCK", what would be the constraint declaration.. Would this be correct:

 

Set output delay -clock [get_clock CLOCK] -clock_rising -add_delay 5.000 [get_port MOSI] ?

 

as for the set_input_delay, if I want the clock to lead the datain by 6 ns  (delay datain from CLOCK) would the following be correct.

 

Set input_delay -clock [get_clock CLOCK] -clock_rising -add_delay 6.000 [get_port DATAIN] ?

There seem to be two more parameters call -min and -max. How are these used? The xilinx explanation is very confusing.

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Moderator
Moderator
1,461 Views
Registered: ‎09-15-2016

Hi @tchin123

 

Please note that -clock_rising is not a valid option with set input or output delay command. Also -add_delay is only used if you want to specify additional delay on the same port and you donot want the to remove the existing delay on the port.

You can simply use this as below:

set_output delay -clock [get_clock CLOCK]  5.000 [get_port MOSI] 

Similarly the set_input_delay command.

Refer below link, page 1378 for information on the syntax:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug835-vivado-tcl-commands.pdf

 

Also max and min values specify setup and hold analysis respectively. If none of them is specified then output and input delay values are applied to both of them .The max and min values are calculated based on the type of interface you are using. For more information you can check language templates in the Vivado GUI.

 

Regards

Rohit

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Regards
Rohit
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Voyager
Voyager
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Registered: ‎05-14-2017

The syntax I used in my example come directly from the Vivado Constraint Wizard. The add delay and max and min parameters are created when the Wizard is used. Their explanation is very confusing and I wasn't sure if the result is what I wanted in the first place.

 

From you answer, if I am sending the CLOCK and MOSI signals out of the FPGA and if I want the MOSI to follow the CLOCK by 5 ns then your example :

set_output delay -clock [get_clock CLOCK]  5.000 [get_port MOSI] 

 

Vivado would provide the 5ns delay on the MOSI and should be used in my constraint file and should work?

 

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Moderator
Moderator
1,424 Views
Registered: ‎09-15-2016

Hi @tchin123

 

Even if you run the set_input_delay command from the Vivado tcl console you will see that -clock_rising is not a valid option.

You can run the below command to achieve your objective:

set_output delay -clock [get_clock CLOCK]  5.000 [get_port MOSI] 

 

If you want to specify different output values for min and max analysis w.r.t to clock then you can specify it as below:

set_output delay -clock [get_clock CLOCK]  max  <max_value> [get_port MOSI] 

set_output delay -clock [get_clock CLOCK]  min <min_value>  [get_port MOSI] 

 

Refer below link, page 100 for more information on this:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug903-vivado-using-constraints.pdf

 

Hope this helps.

 

Regards

Rohit

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Regards
Rohit
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Voyager
Voyager
1,410 Views
Registered: ‎05-14-2017

One question I have on this constraint

 

set_output delay -clock [get_clock CLOCK]  5.000 [get_port MOSI] 

I believed this set the relationship with a delay of 5ns at he pin for the signal MOSI from the CLOCK input at the D-FF, right ?

 

What if I want the 5ns between both signal (MOSI and CLOCK) in the FPGA output PIN level

 

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