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ssampath
Voyager
Voyager
598 Views
Registered: ‎10-12-2016

setup issue because of Clock period variation ?

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Hi Friends,

I am seeing setup issues because of small variation in the clock period of one of clock.

SPI_clk_issue.png

 

Actually both are 50M in the above snap shot,  Required time for setup wrongly showing, how to solve it ?

Any help or suggestions are highly appreciated.

-Sampath

 

-Sampath
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1 Solution

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ssampath
Voyager
Voyager
433 Views
Registered: ‎10-12-2016

Hey Thanks @avrumw , @rshekhaw ,

You are correct, after reading your post i cross checked the clock source paths, they are async. One is coming from Board and other is coming from internal.

Thank you so much for your valuable time.

-Sampath

-Sampath

View solution in original post

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3 Replies
rshekhaw
Xilinx Employee
Xilinx Employee
584 Views
Registered: ‎05-22-2018

Hi @ssampath ,

Will it be possible to share post route dcp?

Thanks,

Raj

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avrumw
Expert
Expert
550 Views
Registered: ‎01-23-2009

There is no way for us to diagnose this without seeing the either the full path or the complete definition of the clocks. Clearly these two clocks are not the same, so this is a clock domain crossing path. The question is, is it a valid synchronous clock domain crossing path, or is it an asynchronous clock domain crossing path - if the latter, then it needs a proper clock domain crossing circuit and an exception.

The best thing is to post the complete static timing path.

Avrum

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ssampath
Voyager
Voyager
434 Views
Registered: ‎10-12-2016

Hey Thanks @avrumw , @rshekhaw ,

You are correct, after reading your post i cross checked the clock source paths, they are async. One is coming from Board and other is coming from internal.

Thank you so much for your valuable time.

-Sampath

-Sampath

View solution in original post

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