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Observer tomikaji
Observer
155 Views
Registered: ‎05-26-2015

signal bus

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Hello,

I have bus 512 lines between to cores. How i can tell vivado to align all bus signal to prevent

data missunderstand. Which constraints should i use for this purpose?

 

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1 Solution

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Historian
Historian
111 Views
Registered: ‎01-23-2009

Re: signal bus

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Your question is very troubling...

If the 512 bus is communicating between two modules that are running on the same clock, then these are normal synchronous paths and there is no risk that the bus will be corrupted between the two modules. No additional constraints are required.

If the bus is going between two different clock domains, then managing the bus skew is absolutely insufficient to ensure that the bus is not corrupted; this is not a matter of constraints, but is a design error.

If data is moving between two different clock domains, then a proper clock domain crossing circuit (CDCC) is required. Each style of CDCC will dictate what kind of timing exceptions are required...

Avrum

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4 Replies
Moderator
Moderator
142 Views
Registered: ‎11-04-2010

Re: signal bus

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Hi, @tomikaji ,

You can consider set_bus_skew constraint.

For the detailed information about the constraint, please refer to UG903.

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Observer tomikaji
Observer
132 Views
Registered: ‎05-26-2015

Re: signal bus

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Ok.

One more thing. Am i correct: in set_bus_skew dialog box from and to fields should be filled with appropriate clock's 

and thought with bus itself? And top field is max skew between all bus signals in ns?

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Historian
Historian
112 Views
Registered: ‎01-23-2009

Re: signal bus

Jump to solution

Your question is very troubling...

If the 512 bus is communicating between two modules that are running on the same clock, then these are normal synchronous paths and there is no risk that the bus will be corrupted between the two modules. No additional constraints are required.

If the bus is going between two different clock domains, then managing the bus skew is absolutely insufficient to ensure that the bus is not corrupted; this is not a matter of constraints, but is a design error.

If data is moving between two different clock domains, then a proper clock domain crossing circuit (CDCC) is required. Each style of CDCC will dictate what kind of timing exceptions are required...

Avrum

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Observer tomikaji
Observer
100 Views
Registered: ‎05-26-2015

Re: signal bus

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Yes you are right. Seems my problem deeper then i thought. I'm going to re-check my design.

 

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